Computer Organization and Architecture (AT70.01) Comp. Sc. and Inf. Mgmt. Asian Institute of Technology

1
Computer Organization and Architecture
(AT70.01)Comp. Sc. and Inf. Mgmt.Asian
Institute of Technology

• Instructor Dr. Sumanta Guha
• Slide Sources Freely downloadable material
  adapted and supplemented

2
Overview of Verilog an HDL (Hardware
Description Language)
3
Verilog

• Verilog is a hardware description language (HDL)
• Verilog is used by several companies in the
  commercial chip design and manufacturing sector
  today. It is rapidly overtaking the rival HDL
  called VHDL
• Verilog allows a designer to develop a complex
  hardware system, e.g., a VLSI chip containing
  millions of transistors, by defining it at
  various levels of abstraction
• at the (highest) behavioral, or algorithmic,
  level the design consists of C-like procedures
  that express functionality without regard to
  implementation
• at the dataflow level the design consist of
  specifying how data is processed and moved
  between registers
• at the gate level the structure is defined as an
  interconnection of logic gates
• at the (lowest) switch level the structure is an
  interconnection of transistors

Register Transfer Level (RTL)
Structural Level
4
Verilog

• Verilog allows the designer to simulate and
  verify the design at each level
• EDA (electronic design automation) tools help the
  designer to move from higher to lower levels of
  abstraction
• Behavioral synthesis tools create dataflow
  descriptions from a behavioral description
• Logic synthesis tools convert an RTL description
  to a switch level interconnection of transistors,
  which is input to an automatic place and route
  tool that creates the chip layout
• With Verilog and EDA tools one could sit at a
  computer at home, design a complex chip, email
  the design to a silicon foundry in California,
  and receive the fabricated chip through regular
  mail in a few weeks!
• The Verilog environment is that of a programming
  language. Designers, particularly with C
  programming experience, find it easy to learn and
  work with

5
Verilog Resources

• Verilog HDL, by Palnitkar (department library)
• Verilog Digital Computer Design Algorithms to
  Hardware, by Arnold (department library)
• John Sanguinetti's Verilog Tutorial
  http//www.vol.webnexus.com/
• Gerard Blair's Verilog Tutorial
  http//www.see.ed.ac.uk/gerard/Teach/Verilog/inde
  x.html
• ALDEC's Verilog Tutorial
• http//www.aldec.com
• DOULOS's Verilog Tutorial
• http//www.doulos.com
• Other on-line resources
• Class website

6
Learning Verilog

• Verilog is essentially a programming language
  similar to C with some Pascal-like constructs
• The best way to learn any programming language is
  from live code
• We will get you started by going through several
  example programs and explaining the key concepts
• We will not try to teach you the syntax
  line-by-line pick up what you need from the
  books and on-line tutorials
• Tip Start by copying existing programs and
  modifying them incrementally making sure you
  understand the output behavior at each step
• Tip The best way to understand and remember a
  construct or keyword is to experiment with it in
  code, not by reading about it
• We shall not design at the switch (transistor)
  level in this course the lowest level we shall
  reach is the gate level. The transistor level is
  more appropriate for an electronics-oriented
  course

7
Example Code

• The example code that follows is mostly from the
  two on-line tutorials or Palnitkars book or
  written in-house. See the source code in the
  Examples directory for authorship information
• All external source code has been downloaded and
  and is available in the Examples directory (see
  class website). Therefore, you can run all the
  examples that follow by using code in that
  directory
• The transparency title shows the source file name
  and (in parentheses) if it is in a sub-directory
  of Examples
• Comments in the original source have often been
  deleted in the transparency and replaced with
  text-box annotation

8
helloWorld.v
Modules are the unit building-blocks (components)
Verilog uses to describe an entire hardware
system. Modules are (for us) of three types
behavioral, dataflow, gate-level. We ignore the
switch-level in this course. This module is
behavioral. Behavioral modules contain code in
procedural blocks.

• module helloWorld
• initial
• begin
• display ("Hello World!!!")
• finish
• end
• endmodule

System calls.
This is a procedural block. There are two types
of procedural blocks initial and always. More
than one statement must be put in a begin-end
group.
9
blocksTime1.v

• module blocksTime1
• integer i, j
• initial
• begin
• i 0
• j 3
• display( "i d, j d", i, j )
• finish
• end
• endmodule

Another behavioral module.
Integer data type other types are time, real and
realtime (same as real).
One initial procedural block.
10
blocksTime2.v

• module blocksTime2
• integer i, j
• initial
• begin
• 2 i 0
• 5 j i
• display( "time d, i d, j d",
  time, i, j )
• end
• initial
• 3 i 2
• initial
• 10 finish
• endmodule

Time delay models signal propagation delay in a
circuit.
Multiple initial blocks. Delays add within each
block, but different initial blocks all start at
time time 0 and run in parallel (i.e.,
concurrently).
11
blocksTime3.v

• module blocksTime3
• integer i, j
• initial
• begin
• 2 i 0
• 5 j i
• display( "time d, i d, j d",
  time, i, j )
• end
• initial
• begin
• 3 i 2
• 2 j i
• display( "time d, i d, j d",
  time, i, j )
• 1 j 8
• display( "time d, i d, j d",
  time, i, j )
• end

Important Verilog is a discrete event
simulator events are executed in a time-ordered
queue.
Multiple initial blocks. Predict output before
you run!
12
blocksTime4.v

• module blocksTime4
• integer i, j
• initial
• begin
• i 0
• j 3
• end
• initial
• 10 finish
• always
• begin
• 1
• i i 1
• j j 1
• display( "i d, j d", i, j )
• end

Always block is an infinite loop. Following are
same always initial
initial begin begin
begin
while(1) forever end
begin begin


end end
end end
Comment out this delay. Run. Explain the problem!
13
clockGenerator.v
Port list. Ports can be of three types
input, output, inout. Each must be declared.

• module clockGenerator(clk)
• output clk
• reg clk
• initial
• begin
• clk 0
• end
• always
• 5 clk clk
• endmodule

Internal register. Register reg data type can
have one of four values 0, 1, x, z. Registers
store a value till the next assignment.
Registers are assigned values in procedural
blocks.
If this module is run stand-alone make sure to
add a finish statement here or simulation will
never complete!
The delay is half the clock period.
14
useClock.v
Compile with the clockGenerator.v module.

• module useClock(clk)
• input clk
• clockGenerator cg(clk)
• initial
• 50 finish
• always _at_(posedge cg.clk) // Bug!! Should work
  with "clk" only instead of
• //
  "cg.clk - Version 9 of Verilogger Pro fixes the
  bug
• display("Time d, Clock up!", time)
• always _at_(negedge cg.clk) //
• display("Time d, Clock down!", time)
• endmodule

Event trigger.
15
systemCalls.v

• module systemCalls(clk)
• input clk
• clockGenerator cg(clk)
• initial
• begin
• 25 stop
• 50 finish
• end
• initial
• begin
• write("write does not ")
• write("add a new line\n")
• display("display does")
• display("add a new line")
• monitor("Clock d", cg.clk) end

Compile with the clockGenerator.v module.
Suspends simulation enters interactive mode.
Terminates simulation.
Similar output calls except display adds a new
line.
monitor produces output each time a variable
changes value.
16
blocksTime5.v

• // Ordering processes without advancing time
• module blockTime5
• integer i, j
• initial
• 0
• display( "time d, i d, j d",
  time, i, j )
• initial
• begin
• i 0
• j 5
• end
• initial
• 10 finish
• endmodule

0 delay causes the statement to execute after
other processes scheduled at that time instant
have completed. time does not advance till after
the statement completes.
Comment out the delay. Run. Explain what happens!
17
blocksTime6.v

• module blocksTime6
• integer i, j
• initial
• begin
• 2 i 0
• j 5 i
• display( "time d, i d, j d",
  time, i, j )
• end
• initial
• 3 i 2
• initial
• 10 finish
• endmodule

Intra-assignment delay RHS is computed
and stored in a temporary (transparent to user)
and LHS is assigned the temporary after the
delay.
Compare output with blocksTime2.v.
18
numbers.v

• module numbers
• integer i, j
• reg30 x, y
• initial
• begin
• i b1101
• display( "decimal i d, binary i b",
  i, i )
• display( "octal i o, hex i h", i, i
  )
• j -1
• display( "decimal j d, binary j b",
  j, j )
• display( "octal j o, hex j h", j, j
  )
• x 4'b1011
• display( "decimal x d, binary x b",
  x, x )
• display( "octal x o, hex x h", x, x
  )
• y 4'd7

Register array.
ltbasegt base can be d, b, o, h
Array of register arrays simulate memory. Example
memory declaration with 1K 32-bit
words reg310 smallMem01023
Default base d
Negative numbers are stored in twos complement
form.
Typical format ltsizegtltbasegtltnumbergt size is a
decimal value that specifies the size of the
number in bits.
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simpleBehavioral.v
Sensitivity trigger when any of a, b or c
changes. Replace this statement with initial.
Output?!
Modules are of three types behavioral, dataflow,
gate-level. Behavioral modules contain code in
procedural blocks. Statements in a procedural
block cannot be re-ordered without affecting the
program as these statements are executed
sequentially, exactly like in a conventional
programming language such as C.

• module aOrNotbOrc(d, a, b, c)
• output d
• input a, b, c
• reg d, p
• always _at_(a or b or c)
• begin
• p a b
• d p c
• end
• endmodule

Ports are of three types input, output,
inout. Each must be declared. Each port also has
a data type either reg or wire (net). Default
is wire. Inputs and inouts are always wire.
Output ports that hold their value are reg,
otherwise wire. More later
One port register, one internal register.
Wires are part of the more general class of nets.
However, the only nets we shall design with are
wires.
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simpleBehavioral.v (cont.)Top-level stimulus
module

• module stimulus
• integer i, j, k
• reg a, b, c
• aOrNotbOrc X(d, a, b, c)
• initial
• begin
• for ( i0 ilt1 ii1 )
• for ( j0 jlt1 jj1 )
• for ( k0 klt1 kk1 )
• begin
• a i
• b j
• c k
• 1 display("a d b d, c d, d
  d", a, b, c, d)
• end
• finish
• end
• endmodule

Verilog Good Design Principle There is one
top-level module, typically called system or
stimulus, which is uninstantiated and has no
ports. This module contains instantiations of
lower-level (inner) sub-modules. Typical picture
below.
Instantiation.
Top-level module
Inner sub-modules
Remove the 1 delay. Run. Explain!
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Port Rules Diagram
Outside connectors to internal ports, i.e.,
variables corresponding to ports in
instantiation of internal module
EXTERNAL MODULE
wire
Example module external reg a wire b internal
in(a, b) //instantiation endmodule module
internal(x, y) input x output y wire x reg
y endmodule
inout
wire
Internal ports
input
output
port-connector
wire
reg or wire
reg or wire

• wire

INTERNAL MODULE
General rule (with few exceptions) Ports in all
modules except for the stimulus module should be
wire. Stimulus module has registers to set data
for internal modules and wire ports only to read
data from internal modules.
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simpleDataflow.v

• module aOrNotbOrc(d, a, b, c)
• output d
• input a, b, c
• wire p, q
• assign q b
• assign p a q
• assign d p c
• endmodule

A dataflow module does not contain
procedures. Statements in a dataflow module can
be re-ordered without affecting the program as
they simply describe a set of data
manipulations and movements rather than a
sequence of actions as in behavioral code. In
this regard dataflow code is very similar to
gate-level code.
Continuous assignment statements any change
in the RHS causes instantaneous update of the
wire on the LHS, unless there is a programmed
delay.
Use stimulus module from behavioral code.
23
simpleGate.v
A gate-level module does not contain
procedures. Statements in a gate-level module
can be re-ordered without affecting the program
as they simply describe a set of connections
rather than a sequence of actions as in
behavioral code. A gate-levelmodule is
equivalent to a combinational circuit.

• module aOrNotbOrc(d, a, b, c)
• output d
• input a, b, c
• wire p, q
• not(q, b)
• or(p, a, q)
• or(d, p, c)
• endmodule

Wire data type can have one of four values 0, 1,
x, z. Wires cannot store values they are
continuously driven.
Primitive gates. Verilog provides several such,
e.g., and, or, nand, nor, not, buf, etc.
Use stimulus module from behavioral code.
24
4valuedLogic.v

• module fourValues( a , b, c, d )
• output a, b, c, d
• assign a 1
• assign b 0
• assign c a
• assign c b
• endmodule
• module stimulus
• fourValues X(a, b, c, d)
• initial
• begin
• 1 display("a d b d, c d, d
  d", a, b, c, d)
• finish
• end
• endmodule

Conflict or race condition. Remember this is not
a procedural (i.e., sequential) block! These
are continuous assign- ments.
4-valued logic 0 low 1 high x unknown z
undriven wire Now explain output!
25
blockingVSnba1.v

• module blockingVSnba1
• integer i, j, k, l
• initial
• begin
• 1 i 3
• 1 i i 1
• j i 1
• 1 display( "i d, j d", i, j )
• 1 i 3
• 1 i lt i 1
• j lt i 1
• 1 display( "i d, j d", i, j )
• finish
• end
• endmodule

Blocking (procedural) assignment the whole
statement must execute before control is
released, as in traditional programming languages.
Non-blocking (procedural) assignment all the
RHSs for the current time instant are evaluated
(and stored transparently in temporaries) first
and, subsequently, the LHSs are updated at the
end of the time instant.
26
blockingVSnba2.v

• module blockingVSnba2(clk)
• input clk
• clockGenerator cg(clk)
• integer i, j
• initial
• begin
• i 10
• 50 finish
• end
• always _at_(posedge clk)
• i i 1 // i lt i 1
• always _at_(posedge clk)
• j i // j lt i
• always _at_(negedge clk)
• display("i d, j d", i, j)
• endmodule

Compile with clockGenerator.v. An application of
non-blocking assignments to solve a race problem.

• With blocking assignments we get different output
  
• depending on the order these two statements are
• executed by the simulator, though they are both
• supposed to execute simultaneously at posedge
  clk
• race problem.
• Race problem is solved if the non-blocking
• assignments (after the comments) are used instead
• - output is unique.

27
blockingVSnba3.v
The most important application of non-blocking
assignments is to model concurrency in hardware
systems at the behavioral level.

• module blockingVSnba3
• reg70 dataBuf, dataCache, instrBuf,
  instrCache
• initial
• begin
• dataCache 8'b11010011
• instrCache 8'b10010010
• 20
• display("Time d, dataBuf b, instrBuf
  b", time, dataBuf, instrBuf)
• dataBuf lt 1 dataCache
• instrBuf lt 1 instrCache
• 1 display("Time d, dataBuf b,
  instrBuf b", time, dataBuf, instrBuf)
• finish
• end
• endmodule

Both loads from dataCache to dataBuf
and instrCache to instrBuf happen concurrently in
the 20-21 clock cycle.
Replace non-blocking with blocking assignments
and observe.
28
4-to-1 multiplexor logic diagram(Folder
Multiplexor)
29
4-to-1 multiplexor (Folder Multiplexor)

• Following are four different Verilog
  implementations of the same multiplexor.
• A stimulus module is shared to test each
  implementation.

30
multiplexor4_1Gate.v(Folder Multiplexor)

• module multiplexor4_1(out, in1, in2, in3, in4,
  cntrl1, cntrl2)
• output out
• input in1, in2, in3, in4, cntrl1, cntrl2
• wire notcntlr1, notcntrl2, w, x, y, z
• not (notcntrl1, cntrl1)
• not (notcntrl2, cntrl2)
• and (w, in1, notcntrl1, notcntrl2)
• and (x, in2, notcntrl1, cntrl2)
• and (y, in3, cntrl1, notcntrl2)
• and (z, in4, cntrl1, cntrl2)
• or (out, w, x, y, z)
• endmodule

Recall default type is wire.
Structural gate-level code based exactly on the
logic diagram.
31
multiplexor4_1Stimulus.v(Folder Multiplexor)

• module muxstimulus
• reg IN1, IN2, IN3, IN4, CNTRL1, CNTRL2
• wire OUT
• multiplexor4_1 mux1_4(OUT, IN1, IN2, IN3,
  IN4, CNTRL1, CNTRL2)
• initial
• begin
• IN1 1 IN2 0 IN3 1 IN4 0
• display("Initial arbitrary values")
• 0 display("input1 b, input2 b,
  input3 b, input4 b\n",
• IN1, IN2, IN3, IN4)
• CNTRL1, CNTRL2 2'b00
• 1 display("cntrl1b, cntrl2b,
  output is b", CNTRL1, CNTRL2, OUT)

Stimulus code that generates test vectors.
Concatenation.
32
multiplexor4_1Stimulus.v (cont., Folder
Multiplexor)

• CNTRL1, CNTRL2 2'b01
• 1 display("cntrl1b, cntrl2b output
  is b", CNTRL1, CNTRL2, OUT)
• CNTRL1, CNTRL2 2'b10
• 1 display("cntrl1b, cntrl2b output
  is b", CNTRL1, CNTRL2, OUT)
• CNTRL1, CNTRL2 2'b11
• 1 display("cntrl1b, cntrl2b
  output is b", CNTRL1, CNTRL2, OUT)
• end
• endmodule

33
multiplexor4_1Logic.v(Folder Multiplexor)

• module multiplexor4_1(out, in1, in2, in3 ,in4,
  cntrl1, cntrl2)
• output out
• input in1, in2, in3, in4, cntrl1, cntrl2
• assign out (in1 cntrl1 cntrl2)
• (in2 cntrl1
  cntrl2)
• (in3 cntrl1
  cntrl2)
• (in4 cntrl1
  cntrl2)
• endmodule

RTL (dataflow) code using continuous assignments
rather than a gate list.
34
multiplexor4_1Conditional.v(Folder Multiplexor)

• module multiplexor4_1(out, in1, in2, in3, in4,
  cntrl1, cntrl2)
• output out
• input in1, in2, in3, in4, cntrl1, cntrl2
• assign out cntrl1 ? (cntrl2 ? in4
  in3) (cntrl2 ? in2 in1)
• endmodule

More RTL (dataflow) code this time using
conditionals in a continuous assignment.
35
multiplexor4_1Case.v(Folder Multiplexor)

• module multiplexor4_1(out, in1, in2, in3, in4,
  cntrl1, cntrl2)
• output out
• input in1, in2, in3, in4, cntrl1, cntrl2
• reg out
• always _at_(in1 or in2 or in3 or in4 or
  cntrl1 or cntrl2)
• case (cntrl1, cntrl2)
• 2'b00 out in1
• 2'b01 out in2
• 2'b10 out in3
• 2'b11 out in4
• default display("Please check
  control bits")
• endcase
• endmodule

Behavioral code output out must now be of reg
type as it is assigned values in a procedural
block.
36
8-to-3 encoder truth table(Folder Encoder)

• Input
  Output
• D7 D6 D5 D4 D3 D2 D1 D0
  A2 A1 A0
• 0 0 0 0 0 0
  0 1 0 0 0
• 0 0 0 0 0 0
  1 0 0 0 1
• 0 0 0 0 0 1
  0 0 0 1 0
• 0 0 0 0 1 0
  0 0 0 1 1
• 0 0 0 1 0 0
  0 0 1 0 0
• 0 0 1 0 0 0
  0 0 1 0 1
• 0 1 0 0 0 0
  0 0 1 1 0
• 1 0 0 0 0 0
  0 0 1 1 1

37
8-to-3 encoder (Folder Encoder)

• Following are four different Verilog
  implementations of the same encoder.
• Each has its own stimulus module.

38
encoder8_3Behavioral.v(Folder Encoder)

• module encoder8_3( encoder_out , enable,
  encoder_in )
• output20 encoder_out
• input enable
• input70 encoder_in
• reg20 encoder_out
• always _at_ (enable or encoder_in)
• begin
• if (enable)
• case ( encoder_in )
• 8'b00000001 encoder_out 3'b000
• 8'b00000010 encoder_out 3'b001
• 8'b00000100 encoder_out 3'b010
• 8'b00001000 encoder_out 3'b011
• 8'b00010000 encoder_out 3'b100
• 8'b00100000 encoder_out 3'b101
• 8'b01000000 encoder_out 3'b110
• 8'b10000000 encoder_out 3'b111
• default display("Check input bits.")

Sensitivity list.
Simple behavioral code using the case statement.
39
encoder8_3BehavioralStimulus.v(Folder Encoder)

• module stimulus
• wire20 encoder_out
• reg enable
• reg70 encoder_in
• encoder8_3 enc( encoder_out, enable, encoder_in
  )
• initial
• begin
• enable 1 encoder_in 8'b00000010
• 1 display("enable b, encoder_in b,
  encoder_out b",
• enable, encoder_in, encoder_out)
• 1 enable 0 encoder_in 8'b00000001
• 1 display("enable b, encoder_in b,
  encoder_out b",
• enable, encoder_in, encoder_out)
• 1 enable 1 encoder_in 8'b00000001
• 1 display("enable b, encoder_in b,
  encoder_out b",
• enable, encoder_in, encoder_out)
• 1 finish
• end

Stimulus for the behavioral code.
Remove this delay. Run. Explain!
40
8-to-3 encoder logic equations(Folder Encoder)

• A0 D1 D3 D5 D7
• A1 D2 D3 D6 D7
• A2 D4 D5 D6 D7

41
encoder8_3structural.v(Folder Encoder)

• module encoder8_3( encoder_out , encoder_in )
• output20 encoder_out
• input70 encoder_in
• or( encoder_out0, encoder_in1,
  encoder_in3, encoder_in5, encoder_in7 )
• or( encoder_out1, encoder_in2,
  encoder_in3, encoder_in6, encoder_in7 )
• or( encoder_out2, encoder_in4,
  encoder_in5, encoder_in6, encoder_in7 )
• endmodule

Structural code. Why is there no enable wire?!
Hint think storage.
42
encoder8_3StructuralStimulus.v(Folder Encoder)

• module stimulus
• wire20 encoder_out
• reg70 encoder_in
• encoder8_3 enc( encoder_out, encoder_in )
• initial
• begin
• encoder_in 8'b00000010
• 1 display("encoder_in b, encoder_out
  b", encoder_in, encoder_out)
• 1 encoder_in 8'b00000001
• 1 display("encoder_in b, encoder_out
  b", encoder_in, encoder_out)
• 1 finish
• end
• endmodule

Stimulus for the structural code.
43
encoder8_3Mixed.v (Folder Encoder)

• module encoder8_3( encoder_out , enable,
  encoder_in )
• output20 encoder_out
• input enable
• input70 encoder_in
• reg20 encoder_out
• wire b0, b1, b2
• or( b0, encoder_in1, encoder_in3,
  encoder_in5, encoder_in7 )
• or( b1, encoder_in2, encoder_in3,
  encoder_in6, encoder_in7 )
• or( b2, encoder_in4, encoder_in5,
  encoder_in6, encoder_in7 )
• always _at_(enable or encoder_in)
• begin
• if (enable) encoder_out b2, b1, b0

Mixed structural-behavioral code. Goal was to
modify structural code to have an enable wire,
which requires register output for storage.
Be careful with mixed design! Its working may
be difficult to understand.
44
encoder8_3MixedStimulus.v(Folder Encoder)

• module stimulus
• wire20 encoder_out
• reg enable
• reg70 encoder_in
• encoder8_3 enc( encoder_out, enable, encoder_in
  )
• initial
• begin
• enable 1 encoder_in 8'b00000010
• 1 display("enable b, encoder_in b,
  encoder_out b",
• enable, encoder_in,
  encoder_out)
• 1 enable 1 encoder_in 8'b00000010
• 1 display("enable b, encoder_in b,
  encoder_out b",
• enable, encoder_in, encoder_out)

Stimulus for the mixed code.
Output is puzzling! Explain!
45
encoder8_3MixedStimulus.v (cont., Folder Encoder)

• 1 enable 0 encoder_in 8'b00000001
• 1 display("enable b, encoder_in b,
  encoder_out b",
• enable, encoder_in, encoder_out)
• 1 enable 1 encoder_in 8'b10000000
• 1 display("enable b, encoder_in b,
  encoder_out b",
• enable, encoder_in, encoder_out)
• 1 finish
• end
• endmodule

46
Comparator modules scheme(Folder Comparator)
47
comparator.v (Folder Comparator)
Comparator makes the comparison A ? B where ? Is
determined by the input greaterNotLess and
returns true(1) or false(0).

• module comparator (result, A, B, greaterNotLess)
• parameter width 8
• parameter delay 1
• input width-10 A, B //
  comparands
• input greaterNotLess // 1 -
  greater, 0 - less than
• output result // 1 if
  true, 0 if false
• assign delay result greaterNotLess ? (A gt
  B) (A lt B)
• endmodule

Parameters that may be set when the module is
instantiated.
48
stimulus.v (Folder Comparator)
Stimulus for the comparator.

• module system
• wire greaterNotLess // sense of
  comparison
• wire 150 A, B // comparand
  values - 16 bit
• wire result //
  comparison result
• // Module instances
• comparator (16, 2) comp (result, A, B,
  greaterNotLess)
• testGenerator tg (A, B, greaterNotLess,
  result)
• endmodule

Parameters being set at module instantiation.
49
testGen.v (Folder Comparator)

• module testGenerator (A, B, greaterNotLess,
  result)
• output 150 A, B
• output greaterNotLess
• input result
• parameter del 5
• reg 150 A, B
• reg greaterNotLess
• task check
• input shouldBe
• begin
• if (result ! shouldBe)
• display("Error! d s d, result
  b", A, greaterNotLess?"gt""lt",
• B, result)
• end
• endtask
• initial begin // produce test
  data, check results

Module that generates test vectors for the
comparator and checks correctness of output.
Task definition a task is exactly like a
procedure in a conventional programming language.
50
testGen.v (cont., Folder Comparator)

• del
• check(0)
• B 0
• greaterNotLess 1
• del
• check(1)
• A 1
• greaterNotLess 0
• del
• check(0)
• finish
• end
• endmodule

Task call
51
Typical Module Components Diagram(now that we
have seen examples of all the components)
Module name, Port list (optional, if there are
ports) Port declarations Parameter list
Declaration of variables (wires, reg, integer
etc.)
Instantiation of inner (lower-level) modules
Structural statements (i.e., assign and gates)
Procedural blocks (i.e., always and initial
blocks)
Tasks and functions
endmodule declaration
52
Clock Reducer (Folder Clock Reducer)

• Divide-by-3 clock reducer. The input to the
  module is a reference clock,
• and the output is a clock signal which has a
  pulse every three cycles of
• the reference clock. The pulse width should be
  the same for both clocks.

Output timing diagram
53
clockReducer.v (Folder ClockReducer)

• module divideBy3 (outClk, inClk)
• parameter delay 1
• input inClk // reference
  clock
• output outClk // stepped down
  clock
• reg ff1, ff2, temp // local storage
• initial begin ff1 0 ff2 1 end
• assign outClk ff2 inClk // output
  assignment
• always _at_(posedge inClk)
• begin
• temp ff1
• ff1 ff2
• ff2 (temp ff2)
• end
• endmodule

Follow the logic of this code by filling out the
following table for successive clock
steps inClk ff1 ff2
temp outClk
54
stimulus.v (Folder ClockReducer)

• module system
• wire slowClk, clk // two clocks
• // Module instances
• divideBy3 d3 (.outClk(slowClk), .inClk(clk))
  // clock divider
• clkGen (10) cg (clk)
  // clock generator
• initial begin
• monitor (stime, " clk b slowClk
  b", clk, slowClk)
• 150 finish
• end
• endmodule

Stimulus.
55
clkGen.v (Folder ClockReducer)

• module clkGen (clk)
• parameter period 2
• output clk
• reg clk
• initial clk 0 // start off
  with 0, so first edge is rising
• always // clock loop
• (period/2) clk clk
• endmodule

Clock pulse generator.
56
Shift Register with Counter (Folder
ShiftCountRegister)

• Implement a shift and count register. A data
  value is shifted in on every clock cycle, on the
  rising edge, and the oldest value is shifted out.
  The shift register is fifo. Count the number of
  ones which are present in the shift register. The
  counter should be 32 bits wide (admitedly, this
  is overkill). The depth of the shift register
  should be parameterized.
• The module ports are
• data input (1 bit), clock (1 bit), data output (1
  bit), counter (32 bits).

57
shiftCountRegister.v (Folder ShiftCountRegister)

• module shiftAndCount (bitOut, count, dataIn,
  clk)
• parameter width 8
• output bitOut // data
  shifted out
• output 310 count // count of
  ones
• input dataIn, clk // inputs
• integer count // the
  counter
• reg bitOut //
  temporary
• reg width-10 lastBits // shift
  register
• initial begin count 0 lastBits 0 end
• always _at_(posedge clk) begin
• bitOut lastBitswidth-1
• lastBits (lastBitsltlt1) dataIn
• if (bitOut gt dataIn)
• count count - 1
• else
• if (bitOut lt dataIn)
• count count 1

Follow the logic of this behavioral code with an
example by hand. Observe that initially lastBits
00000000 and with each dataIn bit coming in
from the right lastBits is shifted left so
bitOut is the leftmost bit.
58
stimulus.v (Folder ShiftCountRegister)

• module system
• wire data, clk // nets to
  connect up the pieces
• wire delayedData // data out of
  the fifo
• wire 310 nOnes // number of ones
  contained in fifo
• // Module instances
• shiftAndCount SandC (delayedData, nOnes,
  data, clk) // shift register
• clkGen (10) cg (clk)
  // generate the clock
  
• testGenerator tg (data, delayedData, nOnes,
  clk) // create data, check result
• endmodule

Stimulus.
59
How the shift register and count change with
input(Folder ShiftCountRegister)

• dataIn lastBits bitOut count
• x 00000000 x 0
• 1 00000001 0 1
• 0 00000010 0 1
• 1 00000101 0 2
• 0 00001010 0 2

60
testGen.v (Folder ShiftCountRegister)

• module testGenerator (dataBit, delayedBit, count,
  clk)
• output dataBit
• input delayedBit
• input 310 count
• input clk
• reg dataBit
• initial begin // produce test
  data, check results
• monitor(time," dataBit b delayedBit
  b", dataBit, delayedBit)
• emitBits(0, 1) // take care of
  first cycle
• emitBits('b10010, 5)
• check(0, 2)
• emitBits('b101101, 6)
• check(0, 5)
• emitBits('b01, 2)
• check(1, 5)
• stop

Module generates test vectors and checks result.
Tasks emitBits, check
61
testGen.v (cont., Folder ShiftCountRegister)

• task emitBits // helper task to emit n bits
• input 70 bits, n // task
  inputs
• begin
• repeat (n) begin // assume
  clk is at negedge
• dataBit bits0 // take just
  the low order bit
• bits bits gtgt 1
• _at_(negedge clk)
• end // leave
  at negative edge
• end
• endtask
• task check
• input bit
• input 310 shouldBe
• begin
• if (delayedBit ! bit)
• display(time," delayed bit is
  b but should be b",
• delayedBit, bit)
• if (count ! shouldBe)

Task definitions.
62
clkGen.v (Folder ShiftCountRegister)

• module clkGen (clk)
• parameter period 2
• output clk
• reg clk
• initial clk 0 // start off
  with 0
• always // clock loop
• (period/2) clk clk
• endmodule

Clock pulse generator.
63
4-bit Adder (Folder 4BitAdder)

• 4-bit adder. It takes two 4-bit operands, inA and
  inB, and produces
• a 4-bit result, sum, and a 1-bit carry. It is
  composed of four
• 1-bit adders, each of which has a carry in as
  well as the two operand inputs

t1
t2
t3
Full 1-bit adder
64
1bitAdder.v (Folder 4BitAdder)

• module adder1 (s, cout, a, b, cin)
• output s, cout
• input a, b, cin
• xor (t1, a, b)
• xor (s, t1, cin)
• and (t2, t1, cin),
• (t3, a, b)
• or (cout, t2, t3)
• endmodule

1-bit full adder module. Refer the circuit
diagram before.
65
4bitAdder.v (Folder 4BitAdder)

• module adder4 (sum, carry, inA, inB)
• output 30 sum
• output carry
• input 30 inA, inB
• adder1 a0 (sum0, c0, inA0, inB0,
  1'b0)
• adder1 a1 (sum1, c1, inA1, inB1,
  c0)
• adder1 a2 (sum2, c2, inA2, inB2,
  c1)
• adder1 a3 (sum3, carry, inA3, inB3,
  c2)
• endmodule

4-bit adder module composed of 4 1-bit adders
modules. Structural code.
66
stimulus.v (Folder 4BitAdder)

• module ex2_1
• wire 30 sum, inA, inB
• wire carry
• adder4 a4 (sum, carry, inA, inB)
• adderTest at (inA, inB, sum, carry)
• endmodule

Stimulus.
67
adderTest.v (Folder 4BitAdder)

• module adderTest (A, B, sum, carry)
• output 30 A, B
• input 30 sum
• input carry
• reg 30 A, B
• integer i, j
• initial begin
• monitor ("A d B d sum d carry
  d", A, B, sum, carry)
• for (i0 ilt16 ii1)
• for (j0 jlt16 jj1)
• begin
• A i
• B j
• 1
• end
• finish
• end

Module generates test vectors.
68
Set-Reset (SR-) latch (unclocked)

• A set-reset latch made from two cross-coupled
• nand gates is a basic memory unit.
• When both Sbar and Rbar are 1, then either one
• of the following two states is stable
• Q 1 Qbar 0
• Q 0 Qbar 1
• and the latch will continue in the current stable
  
• state.
• If Sbar changes to 0 (while Rbar remains at 1),
• then the latch is forced to the exactly one
• possible stable state (a). If Rbar changes to 0
• (while Sbar remains at 1), the latch is forced to
  
• the exactly one possible stable state (b).
• So, the latch remembers which of Sbar or Rbar
• was last 0 during the time they are both 1.

Think of Sbar as S, the inverse of set
(which sets Q to 1), and Rbar as R, the inverse
of reset.
Sbar (set inv.)
Q
n1
n2
Qbar
Rbar (reset inv.)
69
sr_latch.v

• module sr_latch(Q, Qbar, Sbar, Rbar)
• output Q, Qbar
• input Sbar, Rbar
• nand n1(Q, Sbar, Qbar)
• nand n2(Qbar, Rbar, Q)
• endmodule

Set-reset latch gate-level code implementing
logic diagram.
70
sr_latch.v (cont.)

• module Top
• wire q, qbar
• reg set, reset
• sr_latch l1(q, qbar, set, reset)
• initial
• begin
• monitor(time, " set b, reset b, q b,
  qbar b\n", set, reset, q, qbar)
• set 0 reset 0
• 5 set 0 reset 1
• 5 set 0. reset 0
• 5 set 1 reset 0
• 5 set 0 reset 1
• 5 set 0 reset 0
• 5 set 1 reset 0
• // 5 set 1 reset 1
• // 5 set 0 reset 0
• end

Stimulus module.
Explain output!
Uncomment one line after another! Explain!
71
Set-Reset (SR-) latch (clocked)
Sbar
X
r1
Q
n1
clkbar
clk
a
n2
Qbar
Rbar
r2
Y

• Clocked SR-latch
• State can change only when clock is high
• Potential non-deterministic behavior if both
  input Sbar and Rbar are 0

72
clockedSR_latch.v

• module clockedSR_latch(Q, Qbar, Sbar, Rbar, clk)
• //Port declarations
• output Q, Qbar
• input Sbar, Rbar, clkbar
• wire X, Y
• // Gate declarations
• not a(clkbar, clk)
• or r1(X, Sbar, clkbar)
• or r2(Y, Rbar, clkbar)
• nand n1(Q, X, Qbar)
• nand n2(Qbar, Y , Q)
• endmodule

Compile with the clockGenerator.v module.
73
clockedSR_latch.v (cont.)

• module Top
• wire q, qbar, clk
• reg set, reset
• clockedSR_latch cl1(q, qbar, set, reset, clk)
• clockGenerator cg(clk)
• initial
• begin
• 2 set 0 reset 1
• 0 display(" time d, clk b, set b,
  reset b, q b\n", time, clk, set, reset, q)
• 2 set 1 reset 0
• 0 display(" time d, clk b, set b,
  reset b, q b\n", time, clk, set, reset, q)
• 2 set 0 reset 1
• 0 display(" time d, clk b, set b,
  reset b, q b\n", time, clk, set, reset, q)
• 2 set 1 reset 0
• 0 display(" time d, clk b, set b,
  reset b, q b\n", time, clk, set, reset, q)
• end

Stimulus module.
Explain output!
74
D-latch (clocked)
Dbar
D
X
a2
r1
Q
n1
clkbar
clk
a1
n2
Qbar
r2
Y

• Clocked D-latch
• State can change only when clock is high
• Single data input
• No problem with non-deterministic behavior

75
clockedD_latch.v

• module clockedD_latch(Q, Qbar, D, clk)
• //Port declarations
• output Q, Qbar
• input D, clk
• wire X, Y, clkbar, Dbar
• // Gate declarations
• not a1(clkbar, clk)
• not a2(Dbar, D)
• or r1(X, Dbar, clkbar)
• or r2(Y, D, clkbar)
• nand n1(Q, X, Qbar)
• nand n2(Qbar, Y , Q)
• endmodule

Compile with the clockGenerator.v module.
76
clockedD_latch.v (cont.)

• module Top
• wire q, qbar, clk
• reg d
• clockedD_latch dl1(q, qbar, d, clk)
• clockGenerator cg(clk)
• initial
• begin
• 2 d 0
• 0 display(" time d, clk b, d b, q
  b\n", time, clk, d, q)
• 2 d 1
• 0 display(" time d, clk b, d b, q
  b\n", time, clk, d, q)
• 2 d 0
• 0 display(" time d, clk b, d b, q
  b\n", time, clk, d, q)
• 2 d 1
• 0 display(" time d, clk b, d b, q
  b\n", time, clk, d, q)
• 4 d 0

Stimulus module.
Explain output!
77
Negative edge-triggered D-flipflop
sbar
s
cbar
clear
q
clkbar
clk
qbar
r
rbar
d
Negative edge-triggered D-flipflop implemented
using 3 SR latches
78
edge_dff.v

• module edge_dff(q, qbar, d, clk, clear)
• output q,qbar
• input d, clk, clear
• wire s, sbar, r, rbar,cbar
• not (cbar, clear)
• not (clkbar, clk)
• // Input latches
• nand (sbar, rbar, s)
• nand (s, sbar, cbar, clkbar)
• nand (r, rbar, clkbar, s)
• nand (rbar, r, cbar, d)
• // Output latch
• nand (q, s, qbar)
• nand (qbar, q, r, cbar)

• Gate-level D-flipflop
• Negative edge-triggered
• Made from 3 SR-latches (see circuit)
• Extremely important module it is the
• fundamental unit of computer memory!

79
edge_dff.v (cont.)

• module Top
• wire q, qbar, clk
• reg d
• edge_dff ff1(q, qbar, d, clk, clear)
• clockGenerator cg(clk)
• initial
• begin
• clear 0
• 2 d 0
• 0 display(" time d, clk b, d b, q
  b\n", time, clk, d, q)
• 4 d 1
• 0 display(" time d, clk b, d b, q
  b\n", time, clk, d, q)
• 2 d 0
• 0 display(" time d, clk b, d b, q
  b\n", time, clk, d, q)
• 4 d 1
• 0 display(" time d, clk b, d b, q
  b\n", time, clk, d, q)
• 10 d 0

Explain output!
80
How the edge-triggered D-flipflop works - 1
SR-latch
Sbar Rbar Q Qbar 1 0 0
1 0 1 1 0 0
0 1 1 1 1 0 1
1 1 1 0
Table of stable states for the SR-latch
Critical insight If Sbar is fixed at value 1
then the output of the latch (value of Q) can be
changed at most once, no matter how many times
Rbar is changed! Analyze why from the table!
Similarly, if Rbar is fixed at value 1 then the
output of the latch can be changed at most once.
81
How the edge-triggered D-flipflop works - 2
Negative edge-triggered D-flipflop shown made of
3 SR-latches clear wire is omitted for simplicity
Critical insight It is wired so that at a
negative clock edge always one of the two latches
at the back has one of its inputs locked down at
1 so only one change can get through and then the
output of the flip-flop never changes again while
the clock remains 0. Details
82
How the edge-triggered D-flipflop works - 3
(1) While clk1 ? clkbar 0
? Rbar1 0 Sbar20 also,
Sbar1 Rbar2 are uniquely determined depending
on D ? Qbar1 Sbar3 1
Q2 Rbar3 1 ?
SR-latch3 only remembers, but doesnt change its
output
83
How the edge-triggered D-flipflop works - 4
(1) If D1, when clk changes from 1 to 0 ?
clkbar changes from 0 to 1
?
(Sbar1, Rbar1) changes from (0, 0) to (0, 1)

? Qbar1 Sbar3 changes from 1 to 0

? (Sbar2, Rbar2) stays (0, 1)

? (Q2, Qbar2) stays (1,0), i.e.. Rbar3 stays
1 (2) While clk 0
? any change in D( Rbar2) cannot
change output of SR-latch1 as Rbar1 1 fixed

? any change in D cannot change input
Sbar2 0 to SR-latch2
? any change in D cannot
change output Q2 Rbar3 1 (though the state of



SR-latch2 may change)
?
(Sbar3, Rbar3) is fixed at (0, 1)
?
output Q3 is fixed at 1
84
How the edge-triggered D-flipflop works - 5
(1) If D0, when clk changes from 1 to 0 ?
clkbar changes from 0 to 1
?
(Sbar1, Rbar1) changes from (1 ,0) to (1, 1)

? Qbar1 Sbar3 stays 1
?
(Sbar2, Rbar2) changes from (0, 0) to (1, 0)

? (Q2, Qbar2) changes from (1,1) to
(0,1), i.e.. Rbar3 changes from 1 to 0 (2) While
clk 0 ?
any change in D( Rbar2) cannot directly change
output of SR-latch2 as Sbar2 1
?
any change in D cannot change inputs to
SR-latch1
? any change in D cannot
change output of SR-latch1
? any
change in D cannot change Sbar2 1 which remains
fixed
? any change in D cannot
change output of SR-latch2 (even after
propagating


through the circuit)
?
(Sbar3, Rbar3) is fixed at (1, 0)
?
output Q3 is fixed at 0
85
Edge-triggered D-flipflop master-slave design

• Alternate master-slave design of a negative
  edge-triggered D-flipflop follows discussions in
  Appendix B.5 of the text
• Two clocked D-latches are wired in a master-slave
  connection (see Fig. B.15) so that
• when the clock is high, the master D-latch is
  open and accepts the data input while the slave
  D-latch stays closed
• when the clock falls the master is closed but the
  slave opens to accept the output of the master,
  and the output of the slave is the output of the
  D-flipflop
• Notes on our implementation that follows
• clocked D-latch is exactly as before in
  clockedD_latch.v, except a clear wire has been
  added note that the text shows a clocked
  D-latch using nor gates and with no clear wire in
  Fig. B.13
• the D-flipflop is exactly as in Fig. B.15, except
  a clear wire has been added

86
Edge-triggered D-flipflop master-slave design
circuits
Dbar
X
D
a2
Z
r1
r3
Q
n1
clkbar
clk
a1
n2
r2
Y
clear
a3
cbar
Clocked D-latch, exactly as in clockedD_latch.v
with a clear wire added
Q1
D
Q
Master D-latch
Slave D-latch
Qbar
clkbar
clk
Master-slave design D-flipflop
clear
87
edge_dffMasterSlave.v

• // Clocked D-latch as in clockedD_latch.v with a
  clear signal added
• module clockedD_latch(Q, Qbar, D, clk, clear)
• output Q, Qbar
• input D, clk, clear
• wire X, Y, Z, clkbar, Dbar, cbar
• not a1(clkbar, clk)
• not a2(Dbar, D)
• not a3(cbar, clear)
• or r1(X, Dbar, clkbar)
• or r2(Y, D, clkbar)
• or r3(Z, X, clear)
• nand n1(Q, Z, Qbar)
• nand n2(Qbar, Y, Q, cbar)
• endmodule
• // Negative edge-triggered D-flipflop with 2
  D-latches in master-slave relation
• module edge_dff(q, qbar, d, clk, clear)

Use same stimulus code as edge_dffGates.v!
88
Counter (Folder Counter)

• Following is code from Palnitkar Sec. 6.5.3 for a
  binary ripple counter.
• Especially see the dataflow code for the negative
  edge-triggered D-flipflop.
• Synthesize the D-flipflop to a gate-level module
  see earlier edge_dff.v

89
Negative edge-triggered D-flipflop (Folder
Counter)
Negative edge-triggered D-flipflop implemented
using 3 SR latches
90
edge_dffDataflow.v (Folder Counter)

• module edge_dff(q, qbar, d, clk, clear)
• output q,qbar
• input d, clk, clear
• wire s, sbar, r, rbar,cbar
• assign cbar clear
• // Input latches
• assign sbar (rbar s),
• s (sbar cbar clk),
• r (rbar clk s),
• rbar (r cbar d)
• // Output latch
• assign q (s qbar),
• qbar (q r cbar)

Negative edge-triggered D-flipflop made from 3
SR-latches. See previous logic diagram.
91
T(oggle)-flipflop (Folder Counter)
Negative edge-triggered T-flipflop
implemented using a D-flipflop and an inverter
gate toggles every clock cycle
92
t_ff.v (Folder Counter)

• module t_ff(q, clk, clear)
• output q
• input clk, clear
• // Instantiate the edge triggered DFF
• // Complement of output q is fed back.
• // Notice qbar not needed. Empty port.
• edge_dff ff1(q, ,q, clk, clear)
• endmodule

Negative edge-triggered T-flipflop made from a
D-flipflop and an inverter gate. It toggles every
clock cycle.
Empty port.
93
Four-bit ripple counter (FolderCounter)
4-bit ripple counter made from a series of
T-flipflops
94
counter.v (Folder Counter)

• module counter(Q , clock, clear)
• output 30 Q
• input clock, clear
• // Instantiate the T flipflops
• t_ff tff0(Q0, clock, clear)
• t_ff tff1(Q1, Q0, clear)
• t_ff tff2(Q2, Q1, clear)
• t_ff tff3(Q3, Q2, clear)
• endmodule

Counter module from 4 T-flipflops. How does it
work?! The output from tffi is the clock for
tffi1.
95
stimulus.v (Folder Counter)

• module stimulus
• reg CLOCK, CLEAR
• wire 30 Q
• initial
• monitor(time, " Count Q b Clear b",
  Q30,CLEAR)
• counter c1(Q, CLOCK, CLEAR)
• initial
• begin
• CLEAR 1'b1
• 34 CLEAR 1'b0
• 200 CLEAR 1'b1
• 50 CLEAR 1'b0
• end
• initial
• begin

Stimulus module.
Follow the logic of this code by filling out the
following table for successive clock
steps clock tff3 tff2
tff1 tff0 0 0
0 0 0 1 0 1 0
1 0 1 0
96
A Simple Single-Cycle Computer that does Loads
(Folder SimpleSingleCycleComputer)

• Following is code for a simple single-cycle
  computer. This is an extremely important module
  as it shows implementation of a single-cycle
  datapath in Verilog.
• This simple module can be the basis for a
  complete single-cycle computer.

97
Negative edge-triggered D-flipflop with enable
(Folder SimpleSingleCycleComputer)
sbar
s
cbar
clear
q
clock
enable
clk
r
Enable signal anded with clock suppresses write
when it is 0.
rbar
d
98
edge_dffWithEnable.v (Folder SimpleSingleCycleCo
mputer)

• // Negative edge-triggered D-flipflop modified
  from Palnitkar Ch. 6 edge_dff.v code
• // (1) qbar output dropped
• // (2) Write enable signal added - state can
  change only when enable is high
• module edge_dff( q, d, enable, clock, clear )
• output q
• input d, enable, clock, clear
• wire clk, qbar, s, sbar, r, rbar, cbar
• // The enable signal is anded with the clock
• and ( clk, clock, enable )
• not ( cbar, clear )
• not ( clkbar, clk )
• nand ( sbar, rbar, s )
• nand ( s, sbar, cbar, clkbar )

Negative edge-triggered D-flipflop with enable
wire. See previous circuit.
The enable wire works by suppressing the clock.
99
4-to-1 multiplexor (Folder SimpleSingleCycleComput
er)
i0
y0
i1
y1
out
i2
y2
i3
y3
s0n
s1n
s0
s1
100
multiplexor4_1.v (Folder SimpleSingleCycleComputer
)

• module mux4_to_1 ( out, i0, i1, i2, i3, s1, s0 )
• output out
• input i0, i1, i2, i3
• input s1, s0
• wire s1n, s0n
• wire y0, y1,