Memory buffer development

1
Memory buffer development

• S. Butsyk

2
Basic concept
32 bit wide

• Need to store hits from last 64 beam crossings
  according to the BCO
• Fast readout upon trigger decision
• Use set of 64 FIFO with steering logic on the
  input and output

FIFO0
128 word deep
FIFO1
Data IN
FIFO select Reset logic
Data OUT
CLK
FIFO62
FIFO63
Read Address
3
Implementation

• Use standard FIFO Logicore elements with
  relationally placed macros (RPM)
• 64 8-bit buffers for previous BCO storage
• FIFO RST logic activates 1 clock before the data
  from new BCO starts being written
• Global RST issued to all FIFOs on startup
• Current design 7000 cells, 64 RAM blocks
• Can be implemented on the smallest VSX series
  Virtex-4 chip 4VSX25

4
Current test results
BCO
CHIP_ID
root_at_pcleelinux parport ./pport 100000e0
200000e0 300000e0 400000e0 500000e0 500000e0
500000e0 500000e0 700000e1 000000e1 100000e1
200000e1 300000e1 300000e1 300000e1
300000e1 500000e2 600000e2 700000e2 000000e2
100000e2 100000e2 100000e2 100000e2 300000e3
400000e3 500000e3 600000e3 700000e3 700000e3
700000e3 700000e3 100000e4 200000e4 300000e4
400000e4 500000e4 500000e4 500000e4
500000e4 700000e5 000000e5 100000e5 200000e5
300000e5 300000e5 300000e5 300000e5 500000e6
600000e6 700000e6 000000e6 100000e6 100000e6
100000e6 100000e6 700000bf 700000bf 700000bf
700000bf 700000bf 700000bf 700000bf
700000bf root_at_pcleelinux parport
./pport 500000e0 500000e0 500000e0 500000e0
500000e0 500000e0 500000e0 500000e0 70000001
00000001 10000001 20000001 30000001 30000001
30000001 30000001 50000002 60000002 70000002
00000002 10000002 10000002 10000002
10000002 30000003 40000003 50000003 60000003
70000003 70000003 70000003 70000003 10000004
20000004 30000004 40000004 50000004 50000004
50000004 50000004 70000005 00000005 10000005
20000005 30000005 30000005 30000005
30000005 50000006 60000006 70000006 00000006
10000006 10000006 10000006 10000006 30000007
40000007 50000007 60000007 70000007 70000007
70000007 70000007 root_at_pcleelinux parport
./pport 500000e0 500000e0 500000e0 500000e0
500000e0 500000e0 500000e0 500000e0 700000d9
000000d9 100000d9 200000d9 300000d9 300000d9
300000d9 300000d9 500000da 600000da 700000da
000000da 100000da 100000da 100000da
100000da 300000db 400000db 500000db 600000db
700000db 700000db 700000db 700000db 100000dc
200000dc 300000dc 400000dc 500000dc 500000dc
500000dc 500000dc 700000dd 000000dd 100000dd
200000dd 300000dd 300000dd 300000dd
300000dd 500000de 600000de 700000de 000000de
100000de 100000de 100000de 100000de 300000df
400000df 500000df 600000df 700000df 700000df
700000df 700000df root_at_pcleelinux parport
./pport
FIFO 0 FIFO 1 FIFO 2 FIFO 3 FIFO 4 FIFO 5 FIFO
6 FIFO 7

• Spartan 3 xc3s200 have 12 RAM blocks
• 8 FIFO array model is synthesized and tested
• Fake signal is used for Chip_ID and BCO
• Results encouraging, but some problems left to
  fix
• Good news
• FIFO fills and resets correctly
• Bad news
• First hit from FIFO is missing on the readout
• Empty logic does not work properly
• Readout of the memory with 6 hits from each BCO
  shown, Chip_ID - 3 bit counter

Last hit that was written before read
Last valid hit read, repeats after that