ELEC 5970-003/6970-003 (Fall 2006) Low-Power Design of Electronic Circuits (ELEC 5270/6270) Introduction

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ELEC 5970-003/6970-003 (Fall 2006)Low-Power
Design of Electronic Circuits(ELEC
5270/6270)Introduction

• Vishwani D. Agrawal
• James J. Danaher Professor
• Department of Electrical and Computer Engineering
• Auburn University
• http//www.eng.auburn.edu/vagrawal
• vagrawal_at_eng.auburn.edu

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Course Objective

• Low-power is a current need in VLSI design.
• Learn basic ideas, concepts and methods.
• Gain hands-on experience.

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Student Evaluation

• Homework (30) Four
• Class Project (30)
• Student presentation (10)
• Final Exam (30)

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Introduction
Power Consumption of VLSI Chips
Why is it a concern?
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ISSCC, Feb. 2001, Keynote
Ten years from now, microprocessors will run at
10GHz to 30GHz and be capable of processing 1
trillion operations per second about the same
number of calculations that the world's fastest
supercomputer can perform now. Unfortunately,
if nothing changes these chips will produce as
much heat, for their proportional size, as a
nuclear reactor. . . .
Patrick P. Gelsinger Senior Vice
PresidentGeneral Manager Digital Enterprise
Group INTEL CORP.
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VLSI Chip Power Density
Suns
Surface
Hot Plate
Source Intel?
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SIA Roadmap for Processors (1999)
Year 1999 2002 2005 2008 2011 2014
Feature size (nm) 180 130 100 70 50 35
Logic transistors/cm2 6.2M 18M 39M 84M 180M 390M
Clock (GHz) 1.25 2.1 3.5 6.0 10.0 16.9
Chip size (mm2) 340 430 520 620 750 900
Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.5
High-perf. Power (W) 90 130 160 170 175 183
Source http//www.semichips.org
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Defining Low-Power Design

• Design practices that reduce power consumption at
  least by one order of magnitude in practice 50
  reduction is often acceptable.
• General topics
• Algorithms and architectures
• High-level and software techniques
• Gate and circuit-level methods
• Power estimation techniques
• Test power

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Specific Topics in Low-Power

• Power dissipation in CMOS circuits
• Device technology
• Low-power CMOS technologies
• Energy recovery methods
• Circuit and gate level methods
• Logic synthesis
• Dynamic power reduction techniques
• Leakage power reduction
• System level methods
• Microprocessors
• Arithmetic circuits
• Low power memory technology
• Test Power
• Power estimation

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Power in a CMOS Gate
VDD
iDD(t)
Ground
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Power Dissipation in CMOS Logic (0.25µ)
Ptotal (0?1) CL VDD2 tscVDD Ipeak
VDDIleakage
CL
75
5
20
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Power and Energy

• Instantaneous power (Watts)
• P (t ) iDD (t ) VDD
• Peak power (Watts)
• Ppeak Max P (t )
• Average power (Watts)
• Pav ?0T P (t ) dt /
  T
• Energy (Joules)
• E ?0T P (t ) dt

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Components of Power

• Dynamic
• Signal transitions
• Logic activity
• Glitches
• Short-circuit
• Static
• Leakage

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Power of a Transition
Power CVDD2/2
R
C
R
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Logic Activity and Glitches
1
6
2
5
4
3
d1
d1
d2
7
d1
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Low-Power Design Techniques

• Circuit and gate level methods
• Reduced supply voltage
• Adiabatic switching and charge recovery
• Logic design for reduced activity
• Reduced Glitches
• Transistor sizing
• Pass-transistor logic
• Pseudo-nMOS logic
• Multi-threshold gates

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Low-Power Design Techniques

• Functional and architectural methods
• Clock suppression
• Clock frequency reduction
• Supply voltage reduction
• Power down
• Algorithmic and Software methods

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Test Power

• Power grid on a VLSI chip is designed for certain
  current capacity during functional operation
• Average current ? heat dissipation
• Peak current ? noise, ground bounce
• Problem Tests like scan or BIST are
  nonfunctional and may cause higher than the
  functional circuit activity a functionally good
  chip can fail the test.

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Power Estimation Methods

• Spice Accurate but expensive
• Logic-level
• Event-driven simulation
• Statistical
• Probabilistic
• High-level Hierarchical

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Books on Low-Power Design (1)

• L. Benini and G. De Micheli, Dynamic Power
  Management Design Techniques and CAD Tools,
  Boston Springer, 1998.
• T. D. Burd and R. A. Brodersen, Energy Efficient
  Microprocessor Design, Boston Springer, 2002.
• A. Chandrakasan and R. Brodersen, Low-Power
  Digital CMOS Design, Boston Springer, 1995.
• A. Chandrakasan and R. Brodersen, Low-Power CMOS
  Design, New York IEEE Press, 1998.
• J.-M. Chang and M. Pedram, Power Optimization and
  Synthesis at Behavioral and System Levels using
  Formal Methods, Boston Springer, 1999.
• M. S. Elrabaa, I. S. Abu-Khater and M. I.
  Elmasry, Advanced Low-Power Digital Circuit
  Techniques, Boston Springer, 1997.
• R. Graybill and R. Melhem, Power Aware Computing,
  New York Plenum Publishers, 2002.
• S. Iman and M. Pedram, Logic Synthesis for Low
  Power VLSI Designs, Boston Springer, 1998.
• J. B. Kuo and J.-H. Lou, Low-Voltage CMOS VLSI
  Circuits, New York Wiley-Interscience, 1999.
• J. Monteiro and S. Devadas, Computer-Aided Design
  Techniques for Low Power Sequential Logic
  Circuits, Boston Springer, 1997.
• S. G. Narendra and A. Chandrakasan, Leakage in
  Nanometer CMOS Technologies, Boston Springer,
  2005.
• W. Nebel and J. Mermet, Low Power Design in Deep
  Submicron Electronics, Boston Springer, 1997.

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Books on Low-Power Design (2)

• N. Nicolici and B. M. Al-Hashimi,
  Power-Constrained Testing of VLSI Circuits,
  Boston Springer, 2003.
• V. G. Oklobdzija, V. M. Stojanovic, D. M.
  Markovic and N. Nedovic, Digital System Clocking
  High Performance and Low-Power Aspects,
  Wiley-IEEE, 2005.
• M. Pedram and J. M. Rabaey, Power Aware Design
  Methodologies, Boston Springer, 2002.
• C. Piguet, Low-Power Electronics Design, Boca
  Raton Florida CRC Press, 2005.
• J. M. Rabaey and M. Pedram, Low Power Design
  Methodologies, Boston Springer, 1996.
• S. Roudy, P. K. Wright and J. M. Rabaey, Energy
  Scavenging for Wireless Sensor Networks, Boston
  Springer, 2003.
• K. Roy and S. C. Prasad, Low-Power CMOS VLSI
  Circuit Design, New York Wiley-Interscience,
  2000.
• E. Sánchez-Sinencio and A. G. Andreaou,
  Low-Voltage/Low-Power Integrated Circuits and
  Systems Low-Voltage Mixed-Signal Circuits, New
  York IEEE Press, 1999.
• W. A. Serdijn, Low-Voltage Low-Power Analog
  Integrated Circuits, BostonSpringer, 1995.
• S. Sheng and R. W. Brodersen, Low-Power Wireless
  Communications A Wideband CDMA System Design,
  Boston Springer, 1998.
• G. Verghese and J. M. Rabaey, Low-Energy FPGAs,
  Boston springer, 2001.
• G. K. Yeap, Practical Low Power Digital VLSI
  Design, BostonSpringer, 1998.
• K.-S. Yeo and K. Roy, Low-Voltage Low-Power
  Subsystems, McGraw Hill, 2004.

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Other Books Useful inLow-Power Design

• A. Chandrakasan, W. J. Bowhill and F. Fox, Design
  of High-Performance Microprocessor Circuits, New
  York IEEE Press, 2001.
• N. H. E. Weste and D. Harris, CMOS VLSI Design,
  Third Edition, Reading, Massachusetts,
  Addison-Wesley, 2005.
• S. M. Kang and Y. Leblebici, CMOS Digital
  Integrated Circuits, New York McGraw-Hill, 1996.
• E. Larsson, Introduction to Advanced
  System-on-Chip Test Design and Optimization,
  Springer, 2005.
• J. M. Rabaey, A. Chandrakasan and B. Nikolic,
  Digital Integrated Circuits, Second Edition,
  Upper Saddle River, New Jersey Prentice-Hall,
  2003.
• J. Segura and C. F. Hawkins, CMOS Electronics,
  How It Works, How It Fails, New York IEEE Press,
  2004.