TCAM Enabled OnChip Logic Minimization

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TCAM Enabled On-Chip Logic Minimization

Seraj Ahmad Rabi Mahapatra Department of
Computer Science
Texas AM University
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Presentation Outline

• Introduction
• Motivation
• Previous Work
• Problem formulation
• Enhanced TCAM Lookup
• Minimizer Architecture
• Performance Comparison Results
• Conclusion and future work

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Introduction

• Logic Minimization
• To get the minimal representation of a specified
  Boolean function
• Mainly used in logic synthesis to reduce thegate
  count for implementing Boolean functions
• Intractable

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Minimization Algorithms

• Exact Quine,52, McClusky,56
• Espresso-Exact
• Approximate SPAM,81, MINI,74,
  PRESTO,81, Espresso-II,84
• - Require huge computing and memory resources
• - Suitable for off-chip/offline applications

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Emerging Applications of Logic Minimization

• IP Routing Table Reduction
• Access Control List Reduction
• TCAM Power Reduction
• Dynamic HW/SW Partitioning

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What are the Common Characteristics of these
applications?

• On-Chip
• Fast Execution
• Fast Incremental Updates
• Small Footprints
• Data memory Budgeting

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Existing On-Chip Approaches

• ESPRESSO-II BRAYTON 84
• Unate Recursive Paradigm
• ROCM ROMAN, VAHID 2003
• Single Expand Phase
• D1-MERGE D. ALESSANDRI 97
• Distance One Merge, assuming high correlation
• suggested for minimizing ACL
• m-Trie SERAJ AHMAD,
• RABI MAHAPATRA, 04
• Merge with containment in a trie data structure
• Efficient cube insertion/deletion

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Comparison of Performance - Compaction
Average Reduction 30-40
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Comparison of PerformanceExecution Time
Espresso-II gt 6000 sec ROCM gt 8000 sec mTrie
lt 5 sec
Time (in sec)
Routing Tables
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BGP Update Requirement

• In worst case 2000 updates
• 15 milliseconds per updates
• Updates can be route insertion orroute withdrawl
• Updates may be distributed to biggersub-tables

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Incremental Update Performance
Espresso-II gt 700 sec ROCM 0.7 sec mTrie
.6 sec
Time (in sec)
Subtable Size
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Hardware Acceleration

• Tautology Checking in FPGA Cong et. al.
• Improves performance of Espresso-II by
  1.36x-2.94x
• on average
• Codesigned-ROCM ROMAN, VAHID 2003
• Pushes cofactoring, cover, intersection and many
  other frequently occuring loops in Hardware.
• Improves performance of ROCM by 20 times.
• Not adequate
• Hardware Design Details are not discussed.

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TCAM based Hardware Acceleration

• m-Trie uses merge with containment to achieve
  decent compaction and timing
• Merging and Containment can be efficiently
  performed in TCAMs by suitably extending it.
• TCAM used for lookup can also be utilized for
  performing compaction.

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Basic Concepts
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TCAM Cell
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TCAM Architecture
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TCAM Cell Match Operation
0
1
Search Register 0 ? sl0 1
sl10 TCAM - 0 ? d0 0 d11
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TCAM Cell Mismatch Operation
0
1
Search Register 1 ? sl0 0
sl11 TCAM - 0 ? d0 0 d11
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Cover Lookup ( )

• To find out all the cubes in TCAM which
  coversthe specified cube
• Can be performed using the following encoding
  scheme

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Contain Lookup ( )

• To find out all the cubes in TCAM which are
  contained in the specified cube
• Can be performed using the following encoding
  scheme

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Exact Ternary Lookup ( )

• To find out the cube exactly matching the
  specified ternary cube
• 01x001xxx01 matches only 01x001xxx01, it may
  require several memory accesses in conventional
  memory or CAM due to fixed size storages
• Can be performed using in terms of cover and
  contain lookup operation

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Minimizer Architecture
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Cube Insertion
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Cube Deletion
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Experimental Results
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Compaction Performance
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Performance -Execution Time
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Performance Execution Time
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TCAM TABLE SIZES
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Conclusions

• Proposed a hardware architecture for supporting
  m-Trie
• It offers scalable execution time that is100
  times faster than software based m-Trie
• Provides 0.25 microseconds update time
• From case study, it is found that only150x2 TCAM
  entries will be needed for acceptable minimization

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Future Work

• We plan to implement a hardware based logic
  minimizer employing the m-Trie algorithm to
  further enhance the execution and incremental
  update performance
• m-Trie can be suitably enhanced to support
  general purpose logic minimization

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Questions?