A Study of Delay and Power Consumption of Adders Built with Different Logic Styles

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A Study of Delay and Power Consumption of Adders
Built with Different Logic Styles

• Presented
• By
• Xiaoyong Li

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Objectives

• Implementing 1-bit full adder module with
  different logic styles, such as static CMOS,
  TG-CMOS, Differential Cascade Voltage Switch
  Logic(DCVSL), and Domino logic.
• Measuring the delay and power consumption of the
  32-bit ripple-carry adders.
• Measuring the delay and power consumption of the
  32-bit carry-lookahead adders.
• Discussing the simulation results.

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1-bit Full Adder

• The Logics of the Sum and Carry-out
• s x ? y ? C in
• Cout x?y x ? cin y ? cin
• x, y two 1-bit operands
• cin carry-in
• s sum
• cout carry-out

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1-bit Full Adder (Static CMOS)
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1-bit Full Adder(TG-CMOS)
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2-input XOR Gate(TG-CMOS)
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The Sum Logic of 1-bit Full Adder(DCVSL)

from Dr. Reeses ece8273 lecture notes
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The Carryout Logic of 1-bit Full Adder(DCVSL)
from Dr. Reeses ece8273 lecture notes
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1-bit Full Adder (Domino)
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2-input Domino OR Gate
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Transistor Counts of 1-bit Full Adders
Table 1. The Transistor Counts of 1-bit Full
Adders
Static CMOS TG-CMOS DCVSL Domino
Transistor Count 34 36 22 41
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32-bit Ripple-carry Adder
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32-bit Carry Lookahead Adder
16-bit carry lookahead adder
16-bit carry lookahead adder
C0
C16
P12
G12
G02
P02
2-bit carry lookahead generator
P23
G23
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16-bit Carry Lookahead Adder Module
From Koren Text (Chapter 5)
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Circuit Structure Used for Simulations
X
Sum
32-bit adder
Y
Cout
Cin
CLK
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Spectre Simulation Results
Table 2. Power Consumption and Delay of 32-bit
Ripple-carry Adders (50MHz )
Adder Delay (ns) Power (mW) PowerDelay
Static CMOS 6.679 0.965 6.445
TG-CMOS 19.669 1.004 19.748
DCVSL 10.230 1.220 12.481
Domino 6.124 2.479 15.181
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Spectre Simulation Results
Table 3. Power Consumption and Delay of 32-bit
Carry Lookahead Adders (50MHz )
Adder Delay (ns) Power (mW) PowerDelay
Static CMOS 1.392 1.293 1.800
TG-CMOS 2.163 1.129 2.442
DCVSL 1.842 1.917 3.531
Domino 1.125 6.988 7.861
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Spectre Simulation Results
Table 4. The Delay of 32-bit Carry Lookahead
Adders for Different Input Switching Frequencies
unit (ns)
Adder 50 MHz 10 MHz 0.1 MHz
Static CMOS 1.392 1.407 1.409
TG-CMOS 2.163 2.191 2.176
DCVSL 1.842 1.858 1.845
Domino 1.125 1.138 1.142
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Discussions and Conclusions

• For any of the logic style, the delay of 32-bit
  carry lookahead adder is much shorter than that
  of 32-bit ripple-carry adder.
• The rankings of the delay and power consumption
  are not necessarily related to the transistor
  counts.
• TG-CMOS implementation has the longest delay
  since its 1-bit full adder module cannot provide
  enough driving capability. The switching
  activities inside the adder take more time to
  accomplish.
• The delay of the domino logic implementation is
  the shortest due to its single transistor pull up
  network(less drain/source, parasitic capacitance
  at the output node).

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Discussions and Conclusions(Cont.)

• The DCVSL implementation has the second longest
  delay although it has the lowest transistor
  count. The more complex pull down network
  contributes this conclusion( more drain/source
  and parasitic capacitances need to be charge or
  discharged during the switching procedure).
• The 32-bit ripple-carry adder consumes less power
  than the 32-bit carry lookahead adder for any of
  the logic style because of the carry lookahead
  generator circuit.
• TG-CMOS implementation has the least power
  consumption since the switching activity occurs
  less frequently than the other implementations.
  

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Discussions and Conclusions(Cont.)

• The domino logic consumes more power than the
  other three logic styles. The large amount of
  power is consumed during the precharge period.
  (2.72mW for evaluation period and 4.27mW for
  precharge period).
• For a given logic style, the delay and power
  consumption are determined by the input pattern.
• For any of the logic style, the 1-bit full adder
  module can be optimized for either speed or power
  consumption.
• The product of the delay and power consumption is
  the smallest for the static logic style. The
  domino logic is the best choice when the faster
  circuit is required.

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References

• Ahmed M. Shams, Tarek K. Darwish, and Magdy A.
  Bayoumi, Performance Analysis of Low-Power
  1-bit CMOS Full Adder Cells, IEEE Trans. on Very
  Large Scale Integration Systems, Vol.10, No.1,
  pp20-29, February 2002.
• Jan. M. Rabaey, Digital Integrated Circuits A
  Design Perspective , Prentice-Hall Inc., 1996.