The CMP Service CMP 46 avenue Flix Viallet 38031 Grenoble Cedex, France http:cmp'imag'fr

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The CMP ServiceCMP46 avenue Félix
Viallet38031 Grenoble Cedex, Francehttp//cmp.i
mag.fr
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Outline

• Introduction
• Standard Processes
• Deep submicron processes
• MEMS manufacturing
• Assembling
• Design kits
• Assistance to IP exploitation
• Some trends
• Conclusions

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• CMP
• 1981
• industrial quality process lines (University
  process lines
• cannot offer a stable yield)
• design kits to link CAD and MPW, to facilitate
  the design.

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• Customer base development
• Universities / Research Labs
• Industry
• 530 Institutions in 60 countries
• Technical development
• 19811982 launching CMP with NMOS
• 19831984 development of NMOS, launching
  CMOS
• 19841986 development of CMOS
• 19871989 abandon NMOS, increase the
  frequency of CMOS runs
• 19901994 launching Bipolar, BiCMOS, MESFET
  GaAs, HEMT GaAs, advanced CMOS (.5 µ TLM) and
  MCMs
• 19951997 launching CMOS, BiCMOS and GaAs
  compatible MEMS, DOEs, deep-submicron CMOS
  (.25 µ 6LM)
• 1998 launching surface micromachined MEMS,
  abandon MESFET GaAs
• 1999 launching SiGe, .18 µ CMOS
• 2001 .35 µ HBT SiGe BiCMOS, .12 µ CMOS

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Summary of services one stop shop
ICs AMS 0.8 µ CMOS DLP/DLM 0.6 µ CMOS
DLP/TLM 0.35 µ CMOS DLP/TLM (4LM) 0.8 µ
BiCMOS DLP/DLM 0.8 µ SiGe HBT-CMOS
DLP/DLM STMicroelectronics 0.12 µ CMOS
6LM 0.18 µ CMOS 6LM 0.35 µ HBT SiGe
BiCMOS OMMIC 0.2 µ HEMT GaAs HEMT PEREGRINE 0.5
µ CMOS SOI/SOS DLP/TLM MCMs L, C, D,
3D MEMS CMOS, BiCMOS and GaAs compatible
bulk micromachining MUMPs from CRONOS (Europe,
Africa, South America,) CAD Cadence,
Tanner, ARM Design kits 35 kits
Packaging standard packages, customization
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Outline

• Introduction
• Processes
• Deep submicron processes
• MEMS manufacturing
• Assembling
• Design kits
• Assistance to IP exploitation
• Some trends
• Conclusions

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CMOS, BiCMOS, SiGe BiCMOS from
austriamicrosystems
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CMOS 0.6 (CUP) Met. layer(s) 3 Poly layer(s) 2
about 250 digital cells Supply voltage 5V or
3.3V Application High performance
analog/digital process High resistive poly Mixed
signal analog digital, large digital designs
CMOS 0.35 µ CSI 2 Levels Polysilicon, 3 Levels
Metal. 3.3V / 5.0V I/O pads. Peripheral cells
with high driving capability (from 2mA to
24mA) Application Analog, Digital, Mixed A/D,
RF. Density 17 kgates/mm2 Gate Delay 0.10ns
(NAND2 typical) Libraries Digital and Analog
Standard Cells Pads P-Cells.
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SiGe HBT-CMOS 0.8 µ 3 Levels Polysilicon, and 2
Levels Metal. High Resistive Polysilicon. Vertical
HBT NPN Ft 35 GHz in SiGe HBT-CMOS 0.8
µ Planar Spiral Inductors Model for Simulation,
and Characterized Layouts (Layouts and Models are
compatible in BiCMOS SiGe HBT-CMOS) RF Pads
schematics and simulation models. - With or
without ESD protection - Hexagonal pad
opening - Shielding to lower the RC access
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Silicon On Sapphire (SOS)

• 0.5µ CMOS DLP / TLM
• From Peregrine Semiconductor

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Minimum drawn Length 0.5 µ Operating voltage
1.5 Volt -gt 3.6 Volt Double Layer Polysilicon
(High Resistive Poly Option) Triple Layer
Metal MIM capacitor, and thick Metal3 for
inductors Full-Custom Cadence Design-Kit P-cells
MOS transistors, capacitors, resistors,
inductors Maximum Die Size 18.8mm x 19.13mm
359 mm2
New
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Applications
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GaAs HEMT 0.2 µ

• From OMMIC

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• ED02AH technology
• Gallium arsenide technology for microwaves
  circuits,
• P-HEMT transistors of 0.2 µ (enhancement
  depletion mode),
• Diodes, resistors, capacitors, spiral inductors,
  air bridges,via holes.
• Typical applications
• Low power low noise circuits for microwaves
  circuits up to 60 GHz
• Low noise amplifier for the L band
• Low power for digital applications with very high
  speed clock
• Analog functions with digital control

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Outline

• Introduction
• Processes
• Deep submicron processes
• MEMS manufacturing
• Assembling
• Participation
• Design kits
• Assistance to IP exploitation
• Some trends
• Conclusions

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0.18µ CMOS From STMicroelectronics
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HCMOS8D Process Features
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0.12µ CMOS From STMicroelectronics
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• HCMOS9 0.12µ CMOS process features
• Gate length .13µ (drawn), .11µ (effective)
• Triple well
• Power supply 1.2 V
• Multiple Vt transistor offering
• (Ultra low leakage, Low leakage, High speed)
• Threshold voltages (for 3 families above)
• VTN 570/500/380 mV,
• VTP 590/480/390 mV
• Isat (for 3 families above)
• TN _at_ 1.2 V 410/535/680 µA/µm
• TP _at_ 1.2 V 170/240/320 µA/µm

HCMOS9 Interconnect cross-section (6 layers
Metal) Courtesy STMicroelectronics
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SiGe HBT-CMOS 0.35µ From STMicroelectronics
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BiCMOS6G SiGe HBT-CMOS 0.35µ Gate length
0.35 micron Single layer Poly / 5 layers
Metal MIM 2nF/mm2 High res. Poly
1kOhm/sq Thick Metal 5 2.5 micron Ft 45GHz
(Vertical NPN) Nf 0.8dB _at_ 2GHz (Vertical
NPN) Standard Power supplies 3.3V or 5.0V
Cross-section of an SiGe NPN transistor Courtesy
STMicroelectronics
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Outline

• Introduction
• Processes
• Deep submicron processes
• MEMS manufacturing
• Assembling
• Design kits
• Assistance to IP exploitation
• Some trends
• Conclusions

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MEMS technologies at CMP
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Summary

• IC compatible technologies
• Frontside bulk micromachining
• Silicon CMOS et BiCMOS .8µ .6µ
  austriamicrosystems
• GaAs HEMT .2µ ommic
• LIGA UV on CMOS
• CMOS, BiCMOS 0.8µ austriamicrosystems
• MEMS Specific technologies
• Surface micromachining
• MUMPS 2 polys 2µ JDS CRONOS
• 1 polys 2µ MTEC

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Bulk micromachining on CMOS
opening to the naked silicon
CMOS electronics
Suspended parts
cavity
SI wafer
SEM of thermopiles
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Bulk micromachining on CMOS
Bridge Beam Membrane
Gaz flow sensor
Thermopiles
Fingerprint sensor
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Bulk micromachining on GaAs
Inductors
Thermopiles
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Surface micromachining on Silicon
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Surface micromachining on Silicon

• Electrostatic resonator

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Developments LIGA UV on CMOS
Thick copper
Suspended Nickel
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Outline

• Introduction
• Processes
• Deep submicron processes
• MEMS manufacturing
• Assembling
• Design kits
• Assistance to IP exploitation
• Some trends
• Conclusions

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Packaging Service
CMP offers a Complete Assembly Service
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Packages
Ceramic Packages
Plastic Packages
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Packaging Process for MPW Run
Ø 17, 25, 33um Wire bonding (Al or Au)
Ceramic Packaging
Packaging
Plastic Packaging
Sawing
Naked Dies on Blue film
Wafer
Ultrasonic Bonding Thermosonic Bonding
Visual Inspection
Loading in Waffle Pack
Waffle Pack
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Outline

• Introduction
• Processes
• Deep submicron processes
• MEMS manufacturing
• Assembling
• Design kits
• Assistance to IP exploitation
• Some trends
• Conclusions

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Design Kits distributed by CMP
43 Design kits
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Institutions which received Design Kits 1998 -
2001
Total 444
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Institutions which received Design Kits 1998 -
2001
AMS
ST
OMMIC
Pereg.
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Outline

• Introduction
• Processes
• Deep submicron processes
• MEMS manufacturing
• Assembling
• Design kits
• Assistance to IP exploitation
• Some trends
• Conclusions

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Cooperation CMP ARM
CMP distribute ARM core based tools Design
simulation models ARM Developer
Suite Evaluation boards Debug unit
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Outline

• Introduction
• Processes
• Deep submicron processes
• MEMS manufacturing
• Assembling
• Design kits
• Assistance to IP exploitation
• Some trends
• Conclusions

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Evolution of processes
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Evolution of the complexity

• 1.2 800 gates / mm2
• 1.0 1,000 gates / mm2
• 0.8 1,200 gates / mm2
• 0.7 1,500 gates / mm2
• 0.6 3,000 gates / mm2
• 0.35 17,000 gates / mm2
• 0.25 35,000 gates / mm2
• 0.18 75,000 gates / mm2
• 0.12 180,000 gates / mm2

• 7 years 95 - 01
• CMOS BiCMOS

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Feature Size
AMS 0.8µ CMOS 1.2k gates/mm2
AMS 0.6µ CMOS 3k gates/mm2
AMS 0.35µ CMOS 17k gates/mm2
STM 0.25µ CMOS 35k gates/mm2
STM 0.18µ CMOS 80k gates/mm2
STM 0.12µ CMOS 180k gates/mm2
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Outline

• Introduction
• Processes
• Deep submicron processes
• Micromachining program
• Assembling
• Design kits
• Assistance to IP exploitation
• Some trends
• Conclusions

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Conclusions. CMP
started in 1981. complete portfolio (ICs, MCMs,
MEMS, CAD, .). offers the best advanced
processes. ISO 9002 certified
. Cooperation CMC CMP MOSIS to start