CS231 Arithmetic Circuits

1
CS231Arithmetic Circuits
2
Motivation
Arithmetic circuits are excellent examples of
comb. logic design
Time vs. Space Trade-offs Doing things
fast requires more logic and thus more space
Example carry lookahead logic Arithmetic
Logic Units Critical component of processor
datapath Inner-most "loop" of most
computer instructions
3
Number Systems
Representation of Negative Numbers

• Representation of positive numbers same in most
  systems
• Major differences are in how negative numbers are
  represented
• Three major schemes
• sign and magnitude
• ones complement
• twos complement
• Assumptions
• we'll assume a 4 bit machine word
• 16 different values can be represented
• roughly half are positive, half are negative

4
Number Systems
Sign and Magnitude Representation
High order bit is sign 0 positive (or zero), 1
negative Three low order bits is the
magnitude 0 (000) thru 7 (111) Number range for
n bits /-2 -1 Representations for 0
n-1
5
Number Systems
Sign and Magnitude

• Cumbersome addition/subtraction
• Must compare magnitudes to determine sign of
  result

Ones Complement
N is positive number, then N is its negative 1's
complement
n
4
N (2 - 1) - N
2 10000 -1 00001
1111 -7 0111 1000
Example 1's complement of 7
-7 in 1's comp.
Shortcut method simply compute bit wise
complement 0111 -gt 1000
6
Number Systems
Ones Complement

• Subtraction implemented by addition 1's
  complement
• Still two representations of 0! This causes some
  problems
• Some complexities in addition

7
Number Representations
Twos Complement
like 1's comp except shifted one
position clockwise

• Only one representation for 0
• One more negative number than positive number

8
Number Systems
Twos Complement Numbers
n
N 2 - N
4
2 10000 7 0111 1001
repr. of -7
sub
Example Twos complement of 7
4
2 10000 -7 1001 0111
repr. of 7
Example Twos complement of -7
sub
Shortcut method
Twos complement bitwise complement 1 0111 -gt
1000 1 -gt 1001 (representation of -7) 1001 -gt
0110 1 -gt 0111 (representation of 7)
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Number Representations
Addition and Subtraction of Numbers
Sign and Magnitude
4 3 7
0100 0011 0111
-4 (-3) -7
1100 1011 1111
result sign bit is the same as the operands' sign
when signs differ, operation is subtract, sign of
result depends on sign of number with the larger
magnitude
4 - 3 1
0100 1011 0001
-4 3 -1
1100 0011 1001
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Number Systems
Addition and Subtraction of Numbers
Ones Complement Calculations
4 3 7
0100 0011 0111
-4 (-3) -7
1011 1100 10111 1 1000
End around carry
4 - 3 1
0100 1100 10000 1 0001
-4 3 -1
1011 0011 1110
End around carry
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Number Systems
Addition and Subtraction of Binary Numbers
Ones Complement Calculations
Why does end-around carry work? Its
equivalent to subtracting 2 and adding 1
n
n
n
M - N M N M (2 - 1 - N) (M - N)
2 - 1
(M gt N)
n
n
-M (-N) M N (2 - M - 1) (2 - N
- 1) 2 2
- 1 - (M N) - 1
n-1
M N lt 2
n
n
after end around carry
n
2 - 1 - (M N)
this is the correct form for representing -(M
N) in 1's comp!
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Number Systems
Addition and Subtraction of Binary Numbers
Twos Complement Calculations
4 3 7
0100 0011 0111
-4 (-3) -7
1100 1101 11001
If carry-in to sign carry-out then
ignore carry if carry-in differs from carry-out
then overflow
4 - 3 1
0100 1101 10001
-4 3 -1
1100 0011 1111
Simpler addition scheme makes twos complement the
most common choice for integer number systems
within digital systems
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Number Systems
Addition and Subtraction of Binary Numbers
Twos Complement Calculations
Why can the carry-out be ignored?
-M N when N gt M
n
n
M N (2 - M) N 2 (N - M)
n
Ignoring carry-out is just like subtracting 2
n-1
-M -N where N M lt or 2
n
n
-M (-N) M N (2 - M) (2 - N)
2 - (M N) 2
n
n
After ignoring the carry, this is just the right
twos compl. representation for -(M N)!
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Number Systems
Overflow Conditions
Add two positive numbers to get a negative
number or two negative numbers to get a positive
number
-1
-1
0
0
-2
-2
1111
0000
1
1111
0000
1
1110
1110
0001
0001
-3
-3
2
2
1101
1101
0010
0010
-4
-4
1100
3
1100
3
0011
0011
-5
-5
1011
1011
0100
4
0100
4
1010
1010
-6
-6
0101
0101
5
5
1001
1001
0110
0110
-7
-7
6
6
1000
0111
1000
0111
-8
-8
7
7
-7 - 2 7
5 3 -9
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Number Systems
Overflow Conditions
0 1 1 1 0 1 0 1 0 0 1 1 1 0 0 0
1 0 0 0 1 0 0 1 1 1 0 0 1 0 1 1 1
5 3 -8
-7 -2 7
Overflow
Overflow
0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 1
1 1 1 1 1 1 0 1 1 0 1 1 1 1 0 0 0
5 2 7
-3 -5 -8
No overflow
No overflow
Overflow when carry in to sign does not equal
carry out
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Addition/Subtraction

• Half adder

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Addition/Subtraction (Contd)

• Full-adder

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Addition/Subtraction (Contd)

• Decomposed implementation of full-adder circuit

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Addition/Subtraction (Contd)

• Bit-serial adder

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Addition/Subtraction (Contd)

• An n-bit ripple-carry adder
• Problem long delay
• Let delayFA 10ns ? a 32-bit addition takes 320ns

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Addition/Subtraction (Contd)

• 2s complement addition with provision for
  detecting conditions and exception

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Addition/Subtraction (Contd)

• A hierarchical carry-lookahead adder with
  ripple-carry between blocks

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Addition/Subtraction (Contd)

• Adder-subtractor unit

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Multiplication of Positive Numbers
1 1 1 0
Multiplicand M
(14)

1 0 1 1
Multiplier Q
(11)
1 1 1 0
1 1 1 0
0 0 0 0
1 1 1 0
1 1 1 0
Multiplicand M
(14)

1 0 1 1
Multiplier Q
(11)
1 0 0 1 1 0 1 0
Product P
(154)
Manual multiplication algorithm
1 1 1 0
Partial product 1

1 1 1 0
1 0 1 0 1
Partial product 2
0 0 0 0

If qi 1, add the multiplicand (appropriately
shifted) to the incoming partial product, PPi,
to generate the outgoing partial product,
PP(i1). If qi 0, PPi is passed vertically
downward unchanged.
0 1 0 1 0
Partial product 3

1 1 1 0
1 0 0 1 1 0 1 0
(154)
Product P
Combinational array implementation
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Multiplication of Positive Numbers (Contd)

• Array multiplication may be impractical because
  it uses many gates.

Using ripple-carry adder
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Multiplication of Positive Numbers (Contd)

• Sequential circuit multiplier example

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Integer Division (Contd)

• Non-restoring division algorithm example

For signed division, transform them
into positive numbers, use one of the algorithms
above and then change the sign of the result.
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Floating Point Numbers

• A fixed point representation may need a great
  number of digits to represent a practical range
  of numbers. Also, a great deal of hardware is
  needed for manipulations.
• Using only a few digits, floating point
  representation can represent very large and very
  small numbers at the expense of precision.
• Example 6.023 ? 1023

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Floating Point Numbers (Contd)

• Normalization Many different ways to represent a
  number such as 345.1
• 345.1 ? 100,
• 34.51 ? 101,
• 3.451 ? 102,
• .3451 ? 103,
• .03451 ? 104
• This creates problem when making comparisons.
• Normalize the number such that the radix point is
  located in only one possible position. Normally,
  the radix point is placed immediately to the left
  of the leftmost, nonzero digit in the fraction,
  as in .3451 ? 103. What about the number
  zero?
• Hidden bit in base 2, the leading 1 in the
  normalized mantissa is not stored in memory. This
  adds an additional bit of precision to the right
  of the number.

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Floating Point Numbers (Contd)

• Recap Excess representation
• Positive and negative representations of a number
  are obtained by adding a bias to the twos
  complement representation, ignoring any carry out
  of the most significant digit.
• The leftmost bit is the sign (usually 1
  positive 0 negative)
• ?Numerically smaller numbers have smaller bit
  patterns, simplifying comparisons for floating
  point exponents.
• Example Excess-128
• 25 100110012
• -25 011001112
• One representation for zero 0 100000002 0
  100000002
• Largest positive number is 127 111111112
• Largest negative number is 128 000000002

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Floating Point Numbers (Contd)

• 3-bit Integer Representation

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Floating Point Numbers (Contd)

• Floating point example Represent 25410 in a
  normalized base 8 floating point format with a
  sign bit, followed by a 3-bit excess-4 exponent,
  followed by four base 8 digits.
• Step 1 Convert to the target base using the
  remainder method.
• 254/8 31 R 6 31/8 3 R 7
  3/8 0 R 3, thus
• 25410 3768 376 ? 80
• Step 2 Normalize the number in the target base.
• 376 ? 80 .376 ? 83
• Step 3 Fill in the bit fields, with a sign bit
  0 (positive), an exponent of 7 (3 4) as in
  excess-4, and 4-digit fraction .3760
  
• 0 111 . 011 111
  110 000
• (space are shown for clarity, and base point is
  not stored in the computer)

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Floating Point Numbers (Contd)

• Conversion example Convert (9.375 ? 10-2)10 to
  base 2 scientific notation.
• Step 1 Convert from base 10 floating point to
  base 10 fixed point.
• ? (9.375 ? 10-2)10 .0937510
• Step 2 Convert from base 10 fixed point to base
  2 fixed point.
• ? Thus, .0937510 .000112
• Step 3 Convert to normalized base 2 floating
  point.
• ? .000112 .000112 ? 20 1.1 ? 2-4

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Errors in Floating Point Representation

• Notation
• b Base
• s Number of significant digits (not bits)
  in the fraction
• M Largest exponent
• m Smallest exponent
• Previous example on page 41 b 8 s 4 M 3
  m -4
• Five characteristics
• The number of representable numbers
• The largest positive representable number
• The smallest (nonzero) representable number
• The largest gap between two successive numbers
• The smallest gap between two successive numbers

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Errors in Floating Point Representation (Contd)

• Number of representable numbers
• A one positive number and one negative number (0
  is disallowed)
• B (M m) 1 exponents
• C b 1 values for the first digit (0 is
  disallowed)
• D b s-1 for each of the s 1 remaining digits
• E special representation for 0
• Previous example (2 ? ((3 (-4)) 1) ? (8 1)
  ? 8 41) 1 57345

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Errors in Floating Point Representation (Contd)

• The smallest representable number has the
  smallest exponent and the smallest nonzero
  normalized fraction. ? bm . b-1 bm-1
• The largest representable number has the largest
  exponent and the largest fraction. ? bM .
  (1 - b-s)
• The smallest gap is when the exponent is at its
  smallest value and the least significant bit of
  the fraction changes. ? bm . b-s bm - s
• The largest gap is when the exponent is at its
  largest value and the least significant bit of
  the fraction changes. ? bM . b-s bM s

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Errors in Floating Point Representation (Contd)

• Example a sign bit, 2-bit excess-2 exponent,
  3-bit normalized base 2 fraction, and leading bit
  is visible. The representation of zero is the bit
  pattern 000000.
• Number of representable numbers is 33.
• Smallest representable number is bm-1 1/8.
• Largest representable number is bM . (1 - b-s)
  7/4.
• Smallest gap is bm s 1/32.
• Largest gap is bM s 1/4.

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IEEE-754 Floating-Point Standard

• Developed in 1985. It can be supported in
  hardware, or a mixture of hardware and software.

Single precision
0ltElt255 2-126 to 2127
Hidden bit
Double precision
0ltElt2047 2-1022 to 21023
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IEEE-754 Floating-Point Standard (Contd)

• Floating-point normalization

Unnormalized
Normalized
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IEEE-754 Floating-Point Standard (Contd)

• Examples in the IEEE-754 Format

Double-precision
Clean zero
41
IEEE-754 Floating-Point Standard (Contd)

• IEEE-754 conversion example Represent -12.62510
  in single precision IEEE-754 format.
• Step 1 Convert to the target base 2.
• -12.62510 -1100.1012
• Step 2 Normalize the number in base 2.
• -1100.1012 -1.100101 ? 23
• Step 3 Fill in bits.
• Sign bit 1 (negative)
• Exponent is 3 excess-127 ? 3 127 130
  100000102
• Leading 1 of fraction is hidden, thus the final
  bit pattern is
• 1 1000 0010 . 1001 0100 0000 0000
  0000 000

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Arithmetic Floating-Point Operations

• IEEE-754 single-precision rules
• Add/Subtract Rule
• Choose the number with the smaller exponent and
  shift its mantissa right a number of steps equal
  to the difference in exponents.
• Set the exponent of the result equal to the
  larger exponent.
• Perform addition/subtraction on the mantissas and
  determine the sign of the result.
• Normalize the resulting value, if necessary.

43
Arithmetic Floating-Point Operations (Contd)

• Multiply Rule
• Add the exponents and subtract 127.
• Multiply the mantissas and determine the sign of
  result.
• Normalize the resulting value, if necessary.
• Divide Rule
• Subtract the exponents and add 127.
• Divide the mantissas and determine the sign of
  the result.
• Normalize the resulting value, if necessary.

44
Arithmetic Floating-Point Operations (Contd)

• Truncation methods in the previous algorithms,
  the mantissas of initial operands and final
  results are limited to 24 bits, including the
  implicit leading 1. Thus, the extended mantissa
  bits need to be truncated such that the new
  24-bit mantissa approximates the longer version.
  There are three different methods.
• Suppose we want to truncate a fraction from six
  to three bits
• Chopping where all fractions in the range
  0.b-1b-2b-3000 to 0. b-1b-2b-3111 are
  truncated to 0. b-1b-2b-3.
• Von Neumann rounding if the three bits to be
  removed are all 0s, they are simply dropped.
  However, if any of the bits to be removed are 1,
  the least significant bit of the retained bits is
  set to 1. Thus, in our example, all 6-bit
  fractions with b-4b-5b-6 not equal to 000 are
  truncated to 0. b-1b-21.

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Arithmetic Floating-Point Operations (Contd)

• Truncation methods (contd)
• Rounding a 1 is added to the LSB position of the
  bits to be retained if there is a 1 in the MSB
  position of the bits being removed.
• Thus, 0. b-1b-2b-31 . . . Is rounded to 0.
  b-1b-2b-3 0.001, and 0.
  b-1b-2b-30 . . . is rounded to 0. b-1b-2b-3.
• This provides the closest approximation to the
  number being truncated. However, it is the most
  difficult to implement because it requires an
  addition operation and a possible
  renormalization.
• Guard bits during the floating-point operations,
  it is important to retain extra bits, called
  guard bits, to yield maximum accuracy in the
  final results.
• In IEEE-754, rounding method is used using three
  guard bits to be carried along during the
  intermediate steps in performing the operations.
  The first 2 guard bits are the two most
  significant bits of the section of the mantissa
  to be removed. The third bit is the logical OR of
  all bits beyond these first two bits in the full
  representation of mantissa.

46
Arithmetic Floating-Point Operations (Contd)

• Floating-point addition, subtraction unit

47
Arithmetic Floating-Point Operations (Contd)

• Effect of Loss of Precision

48
Arithmetic Logic Unit Design
74181 TTL ALU
49
Arithmetic Logic Unit Design
74181 TTL ALU
Note that the sense of the carry in and out are
OPPOSITE from the input bits
Fortunately, carry lookahead generator maintains
the correct sense of the signals
50
Arithmetic Logic Unit Design
16-bit ALU with Carry Lookahead
51
BCD Addition
BCD Number Representation
Decimal digits 0 thru 9 represented as 0000 thru
1001 in binary
Addition
5 0101 3 0011 1000 8
5 0101 8 1000 1101 13!
Problem when digit sum exceeds 9
Solution add 6 (0110) if sum exceeds 9!
5 0101 8 1000 1101 6
0110 1 0011 1 3 in BCD
9 1001 7 0111 1 0000 16 in
binary 6 0110 1 0110 1 6 in BCD
52
BCD Addition
Adder Design
Add 0110 to sum whenever it exceeds 1001 (11XX or
1X1X)