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Designing a TCP/IP Core for Power Consumption Analysis

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TCP/IP protocol designed by software. Major protocol for network data transactions ... RTL design by using Verilog-HDL. Logic synthesis ... – PowerPoint PPT presentation

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Title: Designing a TCP/IP Core for Power Consumption Analysis


1
Designing a TCP/IP Core for Power Consumption
Analysis
  • Kenichi Tanamachi, Koji Inoue, and Vasily G.
    Moshnyaga
  • Fukuoka University

2
Background
  • TCP/IP protocol designed by software
  • Major protocol for network data transactions
  • Network bandwidth increasingly grows
  • Grow 1Gbps in near future
  • Bottleneck in high-speed network
  • Low-speed TCP/IP packet processing
  • of termination nodes
  • Require low-power for mobile network-connected
    computing devices
  • PDA, Cellular phone,

3
TCP/IP protocol stack
Transmit
Receive
Application layer(HTTP,SMTP,POP3)


Data link layer (Ethernet,PPP)
Data
Data
Data
TCPheader
Data
TCPheader
Data
TCPheader
IPheader
IPheader
Data
TCPheader
IPheader
Ethernet header
Ethernet header
Internet
4
Purpose
Implement TCP/IP packet processing by custom
hardware and analyze its power consumption
  • In order to analyze power consumption
  • Step1 Decide TCP/IP Core organization
  • Step2 Design TCP/IP Core
  • Step3 Analyze the power consumption

5
Design Flow
  • Functional partition
  • -decide functional partition of TCP and IP
  • HDL
  • -RTL design by using Verilog-HDL
  • Logic synthesis
  • -use synopsys Design Compiler with 0.35µm CMOS
    library
  • -output report file for area and power
    consumption
  • Layout
  • -use an auto PR tool
  • -extract wire load capacitance
  • Analysis

HDL
Simulation
Library
Logic Synthesis
Report file
Layout
6
  • TCP Core

7
Functional Partition
Application layer
  • port_ctr (BLOCK1)
  • Transfer data to or from application layer
  • data_ctr (BLOCK2)
  • Divide and reconstruct data by using sequence
    numbers
  • Error check by timer
  • window_ctr (BLOCK3)
  • Congestion control by inform transmit-side
    receive-sides empty buffer size
  • checksum (BLOCK4)
  • Check error of data and header, and if have some
    error, create the request of retransmission

TCP
port_ctr
data_ctr
window_ctr
checksum
IP layer
Data link layer
8
Result(Area)
Transmit-side
Receive-side
?Note Since TCP functions are different between
transmit-side and receive-side, the measurements
have been done by generating each circuit
9
Result(Power consumption)
Transmit-side
Receive-side
10
Result(Wire capacitance)
Transmit-side
Receive-side
11
Design Results
Area Area Power Power Wire capacitance Wire capacitance
transmit receive transmit receive transmit receive
BLOCK1 4 6 6 4 4 3
BLOCK2 27 23 23 30 22 26
BLOCK3 7 10 10 7 9 6
BLOCK4 62 61 61 59 65 65
Checksum in BLOCK4 requires a large number of
transistors
12
  • IP Core

13
Functional Partition
Application layer
  • sevice_info (block1)
  • Inform header information( IPversion, header
    length, packet length, type of service)
  • frag_ctr (block2)
  • Determine whether to fragment or not data. If
    yes, identify each data
  • add_ctr (block3)
  • Determine source and determination address
  • Checksum (block4)
  • Check error in IP header and compute time to live
    for packet

TCP layer
IP
service_info
frag_ctr
add_ctr
checksum
Data link layer
14
Result
  • Power consumption
  • Area

15
Design Results
Power
Area
16
14
block1
29
26
block2
43
47
block3
12
13
block4
Checksum in block3 requires a large number of
transistors
16
Discussion
  • Which block gives a great impact on power?
  • TCP Core
  • Checksum(BLOCK4) More than 60 of all
  • IP Core
  • Checksum(BLOCK3) More than 47 of all

Focus on these two blocks to lower the power
consumption of TCP/IP Core
17
Comparison of TCP with IP
TCP
IP
receive
transmit
3.332
2.1196
3.774
Area(µ?)
19.669
10.7182
18.8503
Power(mW)
The TCP Core includes more complex functions
than the IP Core
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