Automated%20synthesis%20of%20micro-pipelines%20from%20behavioral%20Verilog%20HDL - PowerPoint PPT Presentation

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Automated%20synthesis%20of%20micro-pipelines%20from%20behavioral%20Verilog%20HDL

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micro-pipelines from behavioral Verilog HDL. Ivan Blunno Politecnico di Torino ... Extension of Verilog HDL subset. Data Path and Control Unit optimizations ... – PowerPoint PPT presentation

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Title: Automated%20synthesis%20of%20micro-pipelines%20from%20behavioral%20Verilog%20HDL


1
Automated synthesis of micro-pipelines from
behavioral Verilog HDL
  • Ivan Blunno Politecnico di Torino
  • Luciano Lavagno Università di Udine

2
The target of our work
HDL Specification
Synchronous Data Path
Asynchronous Control Unit
3
Motivation
  • Language-based design key enabler to synchronous
    logic success
  • Use HDL as single language for
  • specification
  • logic simulation and debugging
  • synthesis-layout generation
  • post-layout simulation
  • HDL must support multiple levels of abstraction

4
Control-data partitioning
  • Splitting of asynchronous control and synchronous
    data path
  • Automated insertion of bundling delays

CONTROL UNIT
DATA PATH
request
DATA
delay
acknowledge
5
Control-data partitioning
  • Splitting of asynchronous control and synchronous
    data path
  • Automated insertion of bundling delays

CONTROL UNIT
DATA PATH
request
CK
DATA
delay
acknowledge
6
Control-data partitioning
  • Splitting of asynchronous control and synchronous
    data path
  • Automated insertion of bundling delays

CONTROL UNIT
DATA PATH
request
DATA
delay
ACK
acknowledge
7
Design flow
D.P. synthesis
Behavioral HDL specification
C.U. synthesis
Synthesis (Synopsys-DC)
Synthesis (petrify)
8
HDL choice standard HDL
  • several tools available, broad user basis
  • BUT syntax and semantics oriented to gates, (not
    STGs or BFSMs or process algebra)
  • need to define a subset for synthesis
  • Choice
  • VHDL
  • Verilog

9
Asynchronous Verilog subset
  • Declarations
  • Initialization and main loop
  • Asynchronous Verilog blocks
  • wait statements
  • Block assignments
  • if - else statements

10
Initialization and main loop
  • Module and signal declaration
  • module example(a, b, c, d)
  • input a, b7..0
  • output c, d
  • reg e, f, g11..0
  • Currently only single module synthesized
  • always loop surrounds live behavior
  • initial block defines initialization sequence

11
Asynchronous Verilog blocks
  • Only structured mix of sequencing,
  • concurrency and choice can be specified
  • begin-end for sequencing
  • fork-join for concurrency
  • if-else for input choice

12
WAIT statement
.... wait(start) ....
STG
13
Assignments
RES 0 ...... ...... RES A B
RES
0
A B
RES_out
cmd_RES_0_out
14
Assignments
RES 0 ...... ...... RES A B
15
Assignments STG specification
REG control
load register req
RES_out
RES_in-
RES_in
load register ack
RES_out-
reg 4ph completion
16
Assignments
RES 0 ...... ...... RES A B
RES
0
A B
RES_out
cmd_RES_0_out
17
Assignments STG specification
REG control
load register req
RES_out
RES_in-
RES_in
load register ack
RES_out-
reg 4ph completion
18
IF - ELSE statements
if(RES7 1) ..... else .....
D.P. block diagram
CMP
FF
1
cmp_0
RES7
cmd_cmp_0_out
comparator - FF
19
IF - ELSE statements
if(RES7 1) ..... else .....
D.P. Verilog specification
always _at_(posedge cmd_cmp_0_out)
begin if(RES7 1) cmp_0 1 else cmp_0
0 end
comparator - FF
20
IF - ELSE statements STG specification
PH
trF
trT
IF branch
ELSE branch
PK
trQ
21
IF - ELSE statements
if(RES7 1) ..... else .....
D.P. block diagram
CMP
FF
1
cmp_0
RES7
cmd_cmp_0_out
comparator - FF
22
IF - ELSE statements STG specification
PH
trF
trT
IF branch
ELSE branch
PK
trQ
23
(No Transcript)
24
Example FIR filter
RES z SMP z 4 SMP z - 1 3
(saturating arithmetic)
SMP


SMP
R
R E S
RES

RES
start
C.U.
done
start
done
25
Example FIR filter
always begin wait(start) RES SMP 4 R
R SMP 3 if(RES7 1) RES 0 else
begin if(RES6 1) RES h3F end done
1 wait(!start) done 0 end
SMP


R
R E S
RES

C.U.
done
start
26
Final STG
27
Future work
  • Extension of Verilog HDL subset
  • Data Path and Control Unit optimizations
  • Module interface design automation.
  • Syntax-directed state encoding to speed up
    control unit logic synthesis
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