ECE 501

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ECE 501

• Session 1
• Dr. John G. Weber
• KL-241E
• 229-3182
• John.Weber_at_notes.udayton.edu
• jweber-1_at_who.rr.com
• http//academic.udayton.edu/JohnWeber

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Course Syllabus

• ECE 501 Contemporary Digital Systems

Introduction to sequential logic, state machines,
high-performance digital systems, theory and
application of modern design, alternative
implementation forms and introduction to HDL,
productivity, recurring and non-recurring costs,
flexibility, testability, software drivers, and
hardware/software integration. Prerequisite ECE
215 or equivalent
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Course Outline

• Introduction
• Review of Boolean Algebra and Combinatorial Logic
• HDL Approach to Logic Design
• Introduction to Verilog HDL
• Structural and Behavioral Specification
• Gates and combinatorial logic
• Flip-flops and Registers
• Clocked Circuits
• Simulation
• Procedural Specification
• Module Design and Validation
• Finite State Machines
• Moore and Mealy Machines
• System on a Programmable Chip (SOPC) Introduction

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Laboratory and Tools

• We will use 351G for our lab work
• Altera Quartus II design tools as well as Altera
  MaxPlus II available
• Project boards will be available in a week or so
• Turn in projects and design homework via e-mail
• If I cant compile and run your project, no grade
  will be assigned

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Projects and Grading

• Grades based on homework, mid-term, final, and
  projects
• Course will combine lecture and lab projects
• Projects
• Project 1 16 Bit Carry Look Ahead Adder
• Project 2 - 16 Bit ALU
• Project 3 - 16 Bit Barrel Shifter
• Project 4 - 16 Bit Booth Multiplier
• Project 5 - Serial Port
• Project 6 Digital Filters
• Project 7 Stack Processor
• Projects will be integrated as I/O devices using
  SOPC concepts and will be tested by writing code
  for the embedded processor.
• Each project will consist of a written report
  outlining your design considerations and choices,
  a copy of the verilog files used, simulation
  results and test results. If you have used test
  software, include those files along with a
  description.

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Digital Logic Design

• Predominately deals with binary variables and
  logical operators
• Variables (symbolized by letters of the alphabet)
  assume values 0 or 1
• Three basic logical operations AND, OR, NOT

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Truth Tables
AND
OR
NOT
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Logic Gates
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Boolean Algebra and Logic Gates

• Boolean Algebra provides a formal method to
  manipulate binary variables
• Classical logic design based on developing
  Boolean equations for desired logic functions
• We will briefly review the axioms of Boolean
  Algebra and the basic theorems

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Axiomatic Definition of Boolean Algebra

• Algebraic structure defined by a set of elements,
  B, together with two binary operators, and ,
  satisfying the following (Huntington) postulates
• (a) Closure with respect to the operator
• (b) Closure with respect to the operator
• 2. (a) An identity element with respect to ,
  designated by 0
• x 0 0 x x
• (b) An identity element with respect to ,
  designated by 1
• x 1 1 x x
• 3. (a) Commutative with respect to x y y
  x
• (b) Commutative with respect to x y
  y x
• 4. (a) is distributive over x (y z)
  (x y) (x z)
• (b) is distributive over x (y z)
  (x y) (x z)
• 5. For every element x ? B, there exists an
  element of x ? B (called the complement of x)
  such that
• x x 1
• x x 0
• 6. There exists at least two elements x,y ? B
  such that x ? y

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Comparison of Boolean Algebra to Ordinary Algebra

• Huntington postulates do not include associative
  law. (It is valid for Boolean algebra and can be
  derived from the other postulates)
• The distributive law stated in 4(b) is not valid
  for ordinary algebra
• 3. Boolean algebra does not have additive or
  multiplicative inverses, hence there are no
  subtraction or division operations
• 4. Ordinary algebra does not have a complement
  operation (Postulate 5)
• 5. Ordinary algebra deals with real numbers (an
  infinite set) while two-valued Boolean algebra
  used for logic design uses only two elements0
  and 1
• Duality The postulates have been listed in
  pairs where one element of the pair may be
  obtained from the other by interchanging the
  binary elements and operators. This is called
  duality.

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Basic Theorems
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Proof of Theorem 1(b)
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Boolean Algebra and Logic Design

• Classical logic design involves developing
  Boolean functions representing the desired logic
• Consider the function F x yz

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Gate Implementation of F

• Translating the Boolean representation of the
  function F to logic gates is straightforward

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More Complex Functions and Simplification

• Consider the function G xyz xyz xy

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More Complex Functions and Simplification (Cont)

• From the identities of Boolean algebra
• G xz(y y) xy xz or xy

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Canonical and Standard Forms

• Consider a truth table for our function G

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Deriving Equations

• The AND combination of x,y,and z terms are called
  minterms
• If n is the number of variables, there are 2n
  possible minterms
• Derive equation from the truth table by examining
  all rows where function is one, then OR the
  corresponding minterms together
  e.g. G xyz xyz xyz xyz
• Combining the last two minterms into xy results
  in the first equation we had for G
• As we saw previously, this does not necessarily
  result in the simplest expression
• Normally we try to express Boolean equations in a
  OR of minterms form
• This is sometimes called the sum of products
  form by analogy to ordinary algebra

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Verilog HDL Example

• Verilog module template

//Comment usually file name here module
modulename(port list) parameters port
declarations wire declarations register
declarations submodule instantiations ..text
body. //your verilog code for your function
here endmodule
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Verilog for our Function G
//Sample Function G //functionG.v module
functionG(x,y,z,G) //port declarations input
x,y,z output G //wire declarations wire
x,y,z,G //should not be necessary since declared
as a port //text body G xyz xyz
xy assign G !x!yz !xyz
x!y endmodule
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Full Adder Sample Design

• Consider adding two four-bit numbers, say 0101
  and 1001
• Looking at the example problem, we can build the
  following truth table for a single stage of the
  adder

0101 1001 1110
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Full Adder Equations

• Using the minterm approach
• Sum abcin abcin abcin abcin
• Carry-out abcin abcin abcin abcin

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Verilog HDL for Full Adder Module

• //fulladder.v
• //Full Adder Module using minterm equations
• module fulladder(a,b,cin, sum, cout)
• input a, b, cin
• output sum, cout
• assign sum !a !b cin !a b !cin
  a !b !cin a b cin
• assign cout !a b cin a !b cin
  a b !cin a b cin
• endmodule

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Simulation Results for Full Adder Module
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VERILOG Code Concepts

• Code may be Structural or Behavioral
• Structural code is one-to-one with the logic
  (Build from logic primitivese.g. AND, NOR, NAND,
  XOR, etc. )
• Behavioral code is abstracted (use equations to
  describe behavior of the circuit)
• VERILOG primitives are used to implement
  structural code
• and (output, input1, input2)
• This implements a two-input AND gate

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Structural Code for our Function G

• //Sample Function G
• //functionG.v
• module functionG(x,y,z,G)
• //port declarations
• input x,y,z
• output G
• //wire declarations
• wire minterm1, minterm2, minterm3, xnot, ynot
• //text body G xyz xyz xy
• // previous implementation
• // assign G !x!yz !xyz x!y
• //
• not (xnot, x)
• not (ynot, y)
• and (minterm1, xnot, ynot, z)
• and (minterm2, xnot, y, z)
• and (minterm3, x, ynot)
• or (G,minterm1, minterm2, minterm3)

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Behavioral Code Concept

• Previous example provides structural HDL which is
  one-to-one with the logic
• Can also specify the module by specifying its
  behavior

//fulladder_b module fulladder_b(a, b, cin,
sum, cout) input a, b, cin output sum,
cout assign cout, sum a b cin
//behavioral assignment endmodule
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Behavioral Simulation Results
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A Two-bit Ripple Carry Adder

• If we treat the Full Adder Module as a black box,
  we can use it to make multiple bit adders

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Verilog HDL for Two-bit Ripple Carry Adder

• //add_2_r.v
• //Two-bit ripple carry adder example
• //Uses fulladder module
• module add_2_r(A, B, cin, SUM, cout1)
• input 10 A,B
• input cin
• output 10 SUM
• output cout1
• wire 10 A, B, SUM
• wire cin, cout1
• fulladder FA1(A1, B1, cout0, SUM1, cout1)
• fulladder FA0(A0, B0, cin, SUM0, cout0)
• endmodule

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Assignment 1Due 9/1/2002

• Prove Theorems 1 through 4 algebraically.
• Show that theorems 5 and 6 are true by using a
  truth table.
• Read Chapters 1, 2, and 3 of the text

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Assignment 2Due 9/8/2004

• Develop a four-bit ripple carry adder based on
  the full adder developed in class. Write the
  Verilog HDL and simulate the operation of the
  adder.
• Extend the four-bit ripple carry adder to 16
  bits. Simulate the results.