System design of Active Basestations based on dynamically reconfigurable hardware

1
System design of Active Basestations based
ondynamically reconfigurable hardware

• Athanassios Boulis and Mani B. Srivastava
• UCLA Electrical Engineering Department
• Los Angeles, CA, USA
• June 7, 2000

2
Introduction

• Great interest in dynamically reconfigurable HW
• Mostly SRAM-based FPGAs
• But applications restricted to computing
• speed up computer intensive tasks that change
  over time (e.g., target recognition)
• reconfigurable computers that change their
  architecture according to data processed

3
A new application domain

• Hardly any applications in network systems
• Routers, Basestations, Host Network Interfaces
• Past fixed black boxes
• Future programmable network systems

Wired infrastructure
Active BS1
Active BS2
Uploading encryption algorithm
data
Uploading transcoder from MPEG 2 to custom format
MPEG2 format
Low bandwidth node with custom video format
encrypted data
Custom video format
Node needing extra security
High bandwidth node with MPEG2 format
4
New challenges

• Networked environment raises issues of
• security
• resource management
• universality / platform independence

5
Example An active basestation
Mobile node
Active node or basestation
Controller
data
n/w interface
PPF
PPF
B
B
PPF
Classifier
Collector
A
PPF
PPF transfer
A , C
c
n/w interface
data
A , B , C
a , b , c
Modified Wireless network driver
PPF
PPF
modified data
n/w interface
Different PPF paths for each different flow of
data
Packet Processing Functions that can be uploaded
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Packet Processing Functions

• PPFs are implemented in software (Java) or
  programmable hardware (FPGAs)

PPF library e.g., encryption
CPU
Storage
PPF
Control
Run-time Reconfigurable Hardware
n/w access card
PPF
PPF
wireless network
wireline network
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HW vs. SW PPFs
more
flexibility
universality
performance
less
Software PPFs
Hardware PPFs
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Implementation platform

• Implementation developed on a PC platform running
  Linux
• Wireless links wireless LAN radios
• Reconfigurable hardware Xilinx 6200 FPGA on a
  PCI board

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Implementation hardware PPFs

• Exploit the incremental reconfiguration of Xilinx
  6200 FPGA
• access the reconfiguration registers in random
  order at run time
• Practical implications efficient mobile
  hardware
• Any other FPGA can be used (e.g. Virtex)
• Although with lower granularity in incremental
  reconfiguration

Description of PPF
Controller
Stalled flow of packets
PPF
PPF
Flow of packets
PPF
PPF
Reconfig. H/W
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A more efficient implementation

• An implementation to boost performance and allow
  much harder real time constrains
• will not transfer the data through many busses
  and memories
• will not use the main CPU's resources

HOST
Common bus
e.g., PCMCIA
PPFs
FPGA
Capturing and
Multi ported
Router
memory
classifying tables
PPFs
CPU
RADIO
An Active Network Card
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Example Application 1
Adaptation of multimedia streams(e.g. packet
length adaptation)
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Example Application 2
Internet
sensor node
PPF
FPGA
user node
Active Basestation
Fusion of sensor data
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What did we learn?

• Using the testbed implementation we discovered
  issues in
• security
• resource management
• universality

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Security Issues

• Problem privacy of data
• Simple rules that the system can enforce
• A node can define PPF paths only for packets
  coming from,or going to it
• Problem buggy or malicious PPFs
• bad PPFs must have minimal effect
• not affect the run-time environment
• not access other address spaces
• not hog resources
• Solution for hardware two steps

verifier
FPGA
Before placement Check the proof of the PPF
After placement Sandboxed environment for HW PPFs
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Resource Management Issues

• PPFs will be executed in a resource-constrained
  environment.
• Problems well understood for software PPFs
• The hardware resource manager has the following
  functions
• admission control
• enough space?
• within quota?
• dynamically change quota?
• allocating the CLBs for the PPF
• reallocating existing PPFs

FPGA
FPGA
?
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Resource Management Issues

• How are PPFs represented in order to place them
  on the FPGA?

By their bounding boxes Simpler admission
By every reconfiguration bit used Better space
utilization
FPGA
FPGA

• Multiple precompiled shapes give more flexibility
  in placement Lach

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Universality Issues

• Platform independence is a desirable attribute
• Platform independence is hard to achieve for
  hardware PPFs
• No common reconfiguration bitstream format for
  hardware PPFs
• great diversity of FPGA devices
• High level languages (VHDL) are impractical
• synthesis, place-and-route tools are too slow to
  be used on-line
• Possible solutions
• Some FPGA device architecture may emerge as a de
  facto standard for networked applications
• Intermediate structural format as a netlist of
  modules
• the Java for hardware

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Conclusions

• Programmable network systems provide an
  attractive new application domain for dynamically
  reconfigurable hardware
• Dynamically reconfigurable hardware enables
  mobile hardware datapaths
• supplements well-known mobile software mechanisms
• New challenges for CAD tools and FPGA
  architectures
• security
• resource management
• universality / platform independence

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Backup slideInteracting with a hardware PPF

• Using user defined registers in the design
• the software can access them with memory ops.
• But a synchronization reusability problem

clear bit
clear register
data
data
data
alt. bit
alt. bit
flow
flow
Enable?
Clock rate
Data rate

• Characterize the hardware PPFs with timing
  constraints that are taken into account when
  reading and writing data to hardware PPFs
• Attach 4 bits to the data to help the hardware
  PPF de-interleave successive data words and also
  maintain the correct state.