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PowerAware Video Processing on the Intel XScale Platform

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Based on the Intel 80200EVB evaluation board with larger memory bandwidth ... Running a modified Linux 2.4.19 kernel. ADI/BRH Platform. ADI/BRH Board. Power Algorithm ... – PowerPoint PPT presentation

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Title: PowerAware Video Processing on the Intel XScale Platform


1
Power-Aware Video Processing on the Intel XScale
Platform
  • Alfred Park
  • Ross Piasecki
  • April 17, 2003
  • CS6235 Prof. Pu and Prof. Schwan

2
Agenda
  • Motivation
  • Objectives
  • Background Information
  • Previous Work
  • Intel XScale Architecture
  • Power Algorithms
  • Experimental Parameters
  • Assumptions
  • Results
  • Conclusions
  • Future Work
  • Questions

3
Motivation
  • Availability of new Dynamic Voltage Scaling (DVS)
    technologies (variable voltage) in power-aware
    processors
  • Power utilization involves both frequency and
    voltage scaling
  • Slack period with respect to QoS
  • Importance of power conservation in mobile
    devices

4
Objectives
  • Implement DVS and Dynamic Frequency Scaling (DFS)
    algorithms using real-time handlers
  • Show that power efficiency using both DVS and DFS
    outperforms DFS alone
  • Show that usage of a DVS/DFS algorithm does not
    compromise real-time deadlines
  • Real-Time handlers implemented via KEcho

5
Revised Objectives
  • Due to issues beyond our control (i.e. hardware
    availability and KEcho incompatibilities) we were
    forced to revise our objectives
  • Original objectives without DVS support
  • Although XScale supports DVS changes on-the-fly,
    voltage scaling support is accomplished using 3rd
    party off-board hardware
  • No kernel-level real-time handlers due to KEcho
    issues

6
Background
  • Power Equations
  • Power C x F x V2
  • Power I x V
  • For processors, reduction in power is
    accomplished through a reduction in frequency,
    which can be accompanied by a reduction in
    voltage
  • Reducing clock rate (F) of a processor will
    reduce power consumption linearly
  • A quadratic reduction in power can be attained by
    reducing voltage (V)
  • Hypothesis combining clock rate and voltage
    reductions will net large power efficiency gains!

7
Background (Cont.)
  • DVS and DFS in the context of video decoding
  • Frame rate deadlines
  • Slack periods
  • Jitter

8
Previous Work
  • Our experiments will be heavily based on the work
    presented in Poellabauer and Schwan 2002, which
    describes DFS algorithms on the iPAQ StrongArm
    PDAs
  • Various papers and conference proceedings have
    been published on portable and low-power devices
    utilizing DVS/DFS algorithms
  • The XScale platform is a new platform with very
    little related previous work

9
Intel XScale Architecture
  • Designed from the ground up to be power-aware and
    high performance
  • Utilizes the ARM instruction set for instruction
    compatibility with previous ARM processors
    (StrongARM SA-1110)
  • Advanced power features
  • Variable voltage (can be reduced to as low as
    0.95v)
  • Frequency scaling in software (on-the-fly)
  • Low power modes

10
ADI/BRH Platform
  • Based on the Intel 80200EVB evaluation board with
    larger memory bandwidth
  • Contains the Intel XScale 80200 processor core
  • Core clock rates from 400MHz to 733MHz in 66MHz
    increments
  • Running a modified Linux 2.4.19 kernel

11
ADI/BRH Board
12
Power Algorithm
  • Modes of Operation
  • Aggressive
  • Conservative
  • Frequency Cycling
  • Minimize jitter (i.e. real deadlines, FPS)
  • Interrupts are generated every 250ms
  • Fourth interrupt call checks the real deadlines
  • Slack Buffers
  • Pixel buffer (generic bit-bucket storing future
    frame data)

13
Power Algorithm (Cont.)
14
Experimental Parameters
  • Frame Rate Deadline
  • Width x Height x Frames Per Second
  • e.g. 320 x 240 x 15 1.152 Mpixels/sec
  • Images
  • 18 PPM Files at 24-bit depth each
  • Image Manipulation
  • Real-Time Image Reduction
  • Test effectiveness of aggressive, conservative,
    and cycling models

15
Assumptions
  • Video stream is emulated through a sequence of
    images
  • Arbitrarily large pixel buffer
  • Source data stream is faster than the data
    consumption rate
  • The video stream is random enough not to be
    cached

16
Experimental Results
  • Clock rate changes
  • Slack and real deadline misses
  • Slack (pixel buffer) sizes
  • Throughput (pixels/sec)
  • Pixels processed per frequency setting
  • Power

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Empirical Data
27
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28
Possible DVSDFS Results
  • With conservative estimates

29
Demo
  • Baseline readings
  • Videos

30
Oscilloscope Baseline Current
400MHz Reading
733MHz Reading
31
Demo Videos
32
Conclusions
  • The conservative timing model does not
    necessarily improve deadline miss ratios
  • Although the aggressive mode induces more
    frequency change sequences, the frequent lower
    clock rates pay off with respect to power
    consumption
  • A DVS algorithm can add significant power savings
    without affecting the frame rate

33
Future Work
  • Implementing a DVS algorithm
  • Potential issues
  • Development of alternate power algorithms
  • Improving the aggressive timing model
  • Potential integration with an actual movie player
  • Moving the image reduction algorithm to a kernel
    for cooperation with kernel-level real-time
    handlers (KEcho)
  • Port power/image algorithms to the Intel PXA 250
    PCA processor
  • Potential problems

34
  • Questions???
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