Introduction

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Introduction OverviewASIP Synthesis
Retargetable Code Generation

• M. Balakrishnan

2nd January 2002
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Presentation Outline

• Introduction Motivation
• Architecture Overview
• ASIP Synthesis
• Memory Customization
• Retargetable Code Generation

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Embedded Systems Design

• Application driven
• Hardware as well as software components
• Hardware IP or ASIC
• Software Processor core or ASIP
• Tools for code generation

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Motivation

• Our motivation for organizing this workshop is to
  bring out the key issues involved in the
  following three key steps on one platform.
• ASIP Synthesis
• Memory customization
• Retargetable code generation

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Design Challenge

• Given an application or a set of applications,
  design a system, possibly hardware plus software,
  which meets the constraints of (or optimizes for)
  area, performance and power. This can be achieved
  by
• Defining the design space to be explored
• Understanding the relationships between
  application characteristics and design
• Creating tools for efficient design space
  exploration

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Presentation Outline

• Introduction Motivation
• Architecture Overview ?
• ASIP Synthesis
• Memory Customization
• Retargetable Code Generation

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Processor Architecture
RF
MEM
ALU
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Architecture Variations

• RISC and CISC
• Harvard Architecture
• Specialized ALUs
• Instruction Pipelining
• Cache memory
• VLIW and Superscalar

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RISC Vs CISC
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Harvard Architecture

• Separate buses for instruction and data
• Separate instruction and data memory
• Popular for DSPs

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Multiple ALUs

• Separate ALU for address generation
• Specialized units for floating data types
• Variable latency units
• Data dependency issues
• Data forwarding

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Instruction Pipelining

• Static Dynamic pipeline
• Pipeline stalls due to
• Data dependency
• Resource conflicts
• Pipeline flushing due to branching

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Instruction Pipelining Example
Ins. 1
Ins. 2
Ins. 3
Fetch
Decode
Execute
3 Stage pipeline
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Pipeline stall due to Resource conflict
Ins. 1
Ins. 2
Ins. 3
Pipeline F D
OF
E
Stall
Stall
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Cache Memory

• Memory bandwidth bottleneck
• Temporal and spatial locality of memory accesses
• Cache size and organization

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Advanced Processors

• Attempts to go below 1 cpi
• Increasing instruction level parallelism
• Data dependency and resource constraints
• Compiler extracts parallelism (VLIW)
• Multiple instruction issue (Superscalar)

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VLIW Vs Superscalar
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Presentation Outline

• Introduction Motivation
• Architecture Overview
• ASIP Synthesis ?
• Memory Customization
• Retargetable Code Generation

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Application Specific Instruction Set Processors

• Designed for specific application
• Exploits special characteristics to meet the
  desired constraints
• Efficient for applications like digital signal
  processing, automatic control systems, cellular
  phones etc.

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GPP-ASIP-ASIC
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Flow Diagram of a typical ASIP Design Methodology
Application Design Constraints
Application Analysis
Architectural Design Space Exploration
Instruction Set Generation
Code Synthesis
Hardware Synthesis
Object Code
Processor Description
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ASIP Design Space Exploration

• Code generation Simulator based
• Estimation (Scheduler) based

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Code Generation Simulator based
Retargetable Compiler
Simulator
Application (HLL)
Object Code
Architecture Description
Trace Data
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Estimation based
Architecture Description
Application (HLL)
Profiler
Retargetable Estimator
Performance and other Estimates
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Flow diagram of overall Methodology
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Presentation Outline

• Introduction Motivation
• Architecture Overview
• ASIP Synthesis
• Memory Customization ?
• Retargetable Code Generation

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Memory Customization Issues

• Memory hierarchy
• Memory technology
• SRAM
• DRAM
• Memory organization
• Ports
• Interleaving

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Local Memory Issues

• Cache (compiler transparent) or Scratchpad memory
  (user assigned)
• Cache or scratchpad memory size
• Cache organization
• Unified or split (I-Cache and D-Cache)
• Direct mapped or set associative
• Write through or write back
• Replacement policies

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Application Characteristics

• Data access requirements
• Data access patterns
• Predictability of access patterns
• Temporal and spatial locality
• Time, area and power constraints

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Presentation Outline

• Introduction Motivation
• Architecture Overview
• ASIP Synthesis
• Memory Customization
• Retargetable Code Generation ?

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Retargetable Code Generator Options

• Compiler Compiler Accept a specific
  architecture as input and generate a compiler
  which accepts the application programs
• Retargetable Compiler Accept both the
  application and the architecture (parameters) as
  inputs and directly generates code

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Issues in Retargetable Code Generation

• Architecture design space parameters
• Instruction set Fixed or Custom
• Custom instruction set Application analysis
• Compiler optimization options
• Code generation objectives Area, performance or
  power

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Thanks