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Title: CS1104: Computer Organisation http://www.comp.nus.edu.sg/~cs1104


1
CS1104 Computer Organisation http//www.comp.nus.
edu.sg/cs1104
  • School of Computing
  • National University of Singapore

2
PII Lecture 4 Instruction Set Architecture (ISA)
  • Instruction Set Architecture
  • Concept 1 Data Storage.
  • Concept 2 Memory Addressing Modes.
  • Concept 3 Operations in the Instruction Set.
  • Concept 4 Instruction Formats.
  • Concept 5 Encoding the Instruction Set.
  • Concept 6 Compilers View.

3
PII Lecture 4 Instruction Set Architecture (ISA)
  • Reading Chapter 3 of Pattersons book
  • 3.1 3.5, 3.8, 3.13.
  • Optional reading 3.12.
  • Many of these sections are related to MIPS and
    will be needed again in the next lecture.
  • Acknowledgement part of the materials is taken
    from Dr Samarjits notes.

4
Recap Organisation
5
Recap Code Execution
6
Recap Instruction Execution Cycle
  • Instruction execution cycle fetch, decode,
    execute.
  • Fetch fetch next instruction (using PC) from
    memory into IR.
  • Decode decode the instruction.
  • Execute execute instruction.

7
Instruction Set Architecture
  • Instruction Set Architecture (ISA) an
    abstraction on the interface between the hardware
    and the low-level software.

8
Instruction Set Architecture (2)
  • The ISA includes everything programmers need to
    know to make the machine code work correctly.
  • It allows computer designers to talk about
    functions independently from the hardware that
    performs them.
  • This abstraction allows many implementations of
    varying cost and performance to run identical
    software.

9
Instruction Set Architecture (3)
  • ISA is determined by
  • Organization of programmable storage.
  • Data types and data structures encoding and
    representations.
  • Instruction formats.
  • Instruction (or operation code, opcode) set.
  • Modes of addressing and accessing data items and
    instructions.
  • Exceptional conditions.

10
Instruction Set Architecture (4)
  • Instruction format or encoding
  • how is it decoded?
  • Location of operands and result
  • where other than memory?
  • how many explicit operands?
  • how are memory operands located?
  • which can or cannot be in memory?
  • Data type and size
  • Operations
  • what are supported
  • Successor instruction
  • jumps, conditions, branches
  • Fetch-decode-execute is always done for any
    instruction!

11
Instruction Set Architecture (5)
  • Instruction set language of the machine.
  • More primitive than high-level languages (eg no
    sophisticated control flow).
  • More restrictive instructions.
  • We will study MIPS instruction set, used by NEC,
    Nintendo, Silicon Graphics, Sony.

12
Instruction Set Architecture (6)
  • Assembly language vs. machine language
  • Assembly provides convenient symbolic
    representation, machine language is the
    underlying reality.
  • Example add t0, t2, t3 vs.
    00000001010010110100000000100000
  • Assembly can provide pseudo-instructions
  • Example move t0, t1 exists only in assembly,
    the actual instruction is add t0, t1, zero.
  • When considering performance you should count
    real instructions.

13
Instruction Set Architecture (7)
  • Representing instructions in computer
  • Assembly Language
  • ADD R0, R1, R2 means R0 ?R1 R2

14
Concept 1 Data Storage
15
Memory Organization
  • The main memory can be viewed as a large,
    single-dimension array of memory locations.
  • Each location of the memory has an address, which
    is an index into the array.
  • The memory map on the right contains one byte (8
    bits) in every location.
  • Byte addressing means the index points to a byte
    of memory.

16
Memory Organization (2)
  • A word is unit of transfer between processor and
    memory.
  • Assuming 4-byte words and n-bit address.
  • 2n bytes with byte addresses from 0 to 2n 1.
  • 2n-2 words with byte addresses 0, 4, 8, , 2n
    4.
  • Words are aligned.
  • What are the last two bits of the address of a
    word, if each word contains 4 bytes?

17
Storage Architecture
Operands may be implicit or explicit.
18
Storage Architecture (2)
  • Stack architecture Operands are implicitly on
    top of the stack.
  • Accumulator architecture One operand is
    implicitly in the accumulator (a register).
    Examples IBM 701, DEC PDP-8.
  • General-purpose register architecture Only
    explicit operands.
  • Register-memory architecture (one operand in
    memory). Examples Motorola 68000, Intel 80386.
  • Register-register (or load-store) architecture.
    Examples MIPS, DEC Alpha.
  • Memory-memory architecture All operands in
    memory. Example DEC VAX.

19
Storage Architecture (3)
Stack Accumulator Register (register-memory) Register (load-store)
Push A Load A Load R1,A Load R1,A
Push B Add B Add R3,R1,B Load R2,B
Add Store C Store R3,C Add R3,R1,R2
Pop C Store R3,C
CAB
20
Storage Architecture (4)
  • The following shows the compilation of the
    statement A BC in different architectures.
  • Stack architecture
  • push AddrC TopTop4 StackTopMemoryAddrC
  • push AddrB TopTop4 StackTopMemoryAddrB
  • add StackTop-4StackTopStackTop-4
  • TopTop-4
  • pop AddrA MemoryAddrAStackTop
    TopTop-4
  • Accumulator architecture
  • load AddrB Acc MemoryAddrB, or Acc B
  • add AddrC Acc B MemoryAddrC, or Acc
    B C
  • store AddrA MemoryAddrA Acc, or A B
    C
  • Memory-memory
  • add AddrA, AddrB, AddrC

21
Registers vs. Memory
  • Registers are fast memories in the processor.
  • Data are transferred from memory to registers for
    faster processing.
  • Compiler associates variables in program with
    registers. (What about programs with many
    variables?)

22
General-Purpose Registers
  • More efficient for compilers to use
  • Example (AB)-(BC)-(AD) must be evaluated in a
    fixed order in a stack computer
  • Registers can hold variables and reduce memory
    traffic.
  • Code density improves since registers can be
    named with fewer bits than memory locations.
  • Modern architectures (after 1980) predominantly
    use the load-store register architecture.

23
General-Purpose Registers (2)
  • Registers are limited in number. A typical system
    may have 16 to 32 registers.
  • MIPS assembly language uses 32 registers.

Name Register number Usage
t8-t9 24-25 More temporaries
gp 28 Global pointer
sp 29 Stack pointer
fp 30 Frame pointer
ra 31 Return address
Name Register number Usage
zero 0 Constant value 0
v0-v1 2-3 Values for results and expression evaluation
a0-a3 4-7 Arguments
t0-t7 8-15 Temporaries
s0-s7 16-23 Saved
at (register 1) is reserved for the
assembler. k0-k1 (registers 26-27) are reserved
for the operation system.
24
General-Purpose Registers (3)
  • Classifying general-purpose register computers
  • ALU (Arithmetic-Logic Unit) instruction has two
    or three operands?
  • Add R2, R1 (R2R2R1) or Add R3, R2, R1
    (R3R2R1)
  • How many operands may be memory addresses in an
    ALU instruction?
  • Zero? One? Two? Three?
  • What are the advantages and disadvantages of each
    of these options?

25
Concept 2 Memory Addressing Modes
26
Memory Locations and Addresses
  • Memory is viewed as a large one-dimensional array
    of bits.
  • Group of n bits to store or retrieve in a single
    operation to/from the memory is a word.
  • A word is usually a multiple of bytes and
    typically 2, 4 or 8 bytes. (Recall one byte 8
    bits.)
  • Memory is addressed to access a single word or a
    byte using a distinct address.
  • Given k-bit address, the address space is of size
    2k.
  • 24-bit address generates 224 ( 16,777,216)
    addresses or locations. This is 16M.

27
Memory Locations and Addresses (2)
  • Byte addressability Successive memory addresses
    refer to successive byte locations in the memory.

Word address
Word address
Byte address
Byte address
0 4 2k-4
3 2 1 0
7 6 5 4

2k-1 2k-2 2k-3 2k-4
0 4 2k-4
0 1 2 3
4 5 6 7

2k-4 2k-3 2k-2 2k-1
Little-endian order
Big-endian order
28
Memory Locations and Addresses (3)
  • Big-endian most significant byte first.
  • IBM 360/370, Motorola 68000, MIPS (Silicon
    Graphics), SPARC, HP PA.
  • Little-endian least significant byte first.
  • Intel 80x86, DEC VAX, DEC Alpha.

Example 0xDEADBEEF
Big-endian Most significant byte first DE AD BE
EF. Little-endian Least significant byte first
EF BE AD DE.
29
Memory Locations and Addresses (4)
  • Word alignment Words are aligned in memory if
    they begin at a byte address that is a multiple
    of the number of bytes in a word.

Example If a word consists of 4 bytes, then
30
Memory Operations
  • Load (Read/Fetch) Transfers the contents of a
    specific memory location to the processor. The
    processor sends address to the memory, and the
    memory reads data at that address and sends to
    processor.
  • Store (Write) Data from the processor is written
    at a specified memory location. Processor sends
    address and data to the memory.

31
Memory Operations (2)
32
Addressing Modes
33
Addressing Modes (2)
  • Register (direct) mode

op opcode rs first source register rt second
source register rd destination register
Example ADD r3, r1, r2
34
Addressing Modes (3)
  • Immediate mode

op opcode rs source register rt destination
register immed constant
Example ADDI r3, r1, 12
35
Addressing Modes (4)
  • Displacement mode

Example LOAD r1, 100(r2)
r2 150 100(r2) 88
36
Addressing Modes (5)
  • Important addressing modes Register, immediate,
    displacement, register indirect. Account for 88
    of workload.
  • Typical displacement size 12 to 16 bits.
  • Typical immediate size 8 to 16 bits.

37
Concept 3 Operations in the Instruction Set
38
Standard Operations in an Instruction Set
39
Frequently Used Instructions
40
Operation Summary
  • Most widely used instructions are simple
    instructions
  • load
  • store
  • add
  • subtract
  • move register-register
  • and
  • shift
  • compare equal, compare not equal
  • branch
  • jump
  • call
  • return

Make these instructions fast! Amdahls law make
the common case fast!
Application domains like media processing
might require additional, different operations
which might not be commonly used in desktop
applications. So the two instruction sets will be
different.
41
Instructions for Control Flow
  • Branch conditional (if ltconditiongt go to
    ltaddressgt)
  • Jump unconditional (go to ltaddressgt)
  • Procedure calls/returns

42
Instructions for Control Flow (2)
  • Addressing modes for control-flow instructions
  • PC-relative destination address displacement
    value in PC(When target address is near the
    current instruction, it requires only a few bit.
    Code can run independently of where it is loaded
    position independence.)
  • Register indirect jumps a register is specified,
    which will contain the target address.(Value in
    the specified register is usually not known at
    compile time, but is computed at run time.)

43
Concept 4 Instruction Formats
44
Instruction Length
  • Variable-length instructions.
  • Intel 80x86 Instructions vary from 1 to 17 bytes
    long.
  • Digital VAX Instructions vary from 1 to 54 bytes
    long.
  • Require multi-step fetch and decode.
  • Allow for a more flexible (but complex) and
    compact instruction set.

45
Instruction Length (2)
  • Fixed-length instructions.
  • Used in most RISC (Reduced Instruction Set
    Computers)
  • MIPS, PowerPC Instructions are 4 bytes long.
  • Allow for easy fetch and decode.
  • Simply pipelining and parallelism.
  • Instruction bits are scarce.
  • Hybrid instructions a mix of variable- and
    fixed-length instructions.

46
Instruction Fields
  • An instruction consist of opcode and a certain
    number (possible zero) of operands.
  • Each instruction has a unique opcode, but
  • How many operands?
  • Are the operands registers or memory?
  • Current high-end processors allow for three
    register operands.
  • Hence if there are 32 registers, then 3 x 5 15
    bits are used up for the operands.
  • For every direct memory operand, at least one
    operand will be taken away.
  • Example LOAD/STORE instructions only have two
    operands.

47
Type and Size of Operands
  • Encoding in the opcode designates the type of an
    operand.
  • Add R3, R2, R1
  • Character (8 bits), half-word (eg 16 bits), word
    (eg 32 bits), single-precision floating point
    (eg 1 word), double-precision floating point
    (eg 2 words).
  • Expectations from any new 32-bit architecture
  • Support for 8-, 16- and 32-bit integer and 32-bit
    and 64-bit floating point operations. A 64-bit
    architecture would need to support 64-bit
    integers as well.
  • Refers to additional notes on the course website
    on 32-bit architecture.

48
Concept 5 Encoding the Instruction Set
49
Instruction Encoding
  • How are instructions represented in binary format
    for execution by the processor?
  • Issues
  • Code size, speed/performance, design complexity.
  • Things to be decided
  • Number of registers
  • Number of addressing modes
  • Number of operands in an instruction
  • The different competing forces
  • Have many registers and addressing modes
  • Reduce code size
  • Have instruction length that is easy to handle
    (fixed-length instructions are easy to handle)

50
Instruction Encoding (2)
  • Three encoding choices variable, fixed, hybrid.

51
Encoding for Fixed-Length Instructions
  • How to fit multiple sets of instruction types
    into a fixed-length instruction format? Work out
    the most constrained set first.
  • An expanding opcode scheme is one where the
    opcode has variable lengths for different
    instructions. This maximizes the instruction
    bits.
  • Example Given a fixed-length instruction set
    where each instruction contains 16 bits. Some
    instructions (call it type-A) require 2 operands,
    while other instructions (call it type-B) require
    only 1 operand. Each operand takes up 5 bits.

52
Encoding for Fixed-Length Instructions (2)
  • If we assume the all opcodes must have the same
    size, to allow for the maximum number of
    instructions, the opcodes must be 6 bits long.
  • We see that there are wasted bits, and the
    maximum total number of instructions is 26 or 64.

53
Encoding for Fixed-Length Instructions (3)
  • If we allow the opcode for type-B instructions to
    be 11 bits long, we may have a bigger set of
    instructions.
  • This is known as expanding opcode.
  • Encoding concern The first 6 bits of the opcode
    for any type-B instruction must not be identical
    to the opcode of any of the type-A instructions.
    (Why?)

54
Encoding for Fixed-Length Instructions (4)
  • What is the maximum total number of instructions
    possible?
  • Answer 1 (26 1) 25 1 6332 2017.
  • How? Let there be 1 type-A instruction (assume
    the opcode is 000000 the choice is arbitrary),
    then there are (26 1) valid patterns for the
    first 6 bits of the type-B instructions, followed
    by any 5 bits.

55
Encoding for Fixed-Length Instructions (5)
  • Design an expanding opcode for the following to
    be encoded in a 36-bit instruction format. An
    address takes up 15 bits and a register number 3
    bits.
  • 7 instructions with two addresses and one
    register number.
  • 500 instructions with one address and one
    register number.
  • 50 instructions with no address or register.

56
Encoding for Fixed-Length Instructions (6)
  • One possible answer is

57
Concept 6 Compilers View
58
Considerations for Compiler
  • Ease of compilation.
  • Orthogonality no special registers, few special
    cases, all operand modes available with any data
    type or instruction type.
  • Completeness support for a wide range of
    operations and target applications.
  • Regularity no overloading for the meanings of
    instruction fields.
  • Streamlined resource needs easily determined.

59
Considerations for Compiler (2)
  • Provide at least 16 general-purpose registers
    plus separate floating-point registers.
  • Be sure all addressing modes apply to all data
    transfer instructions.
  • Aim for a minimalist instruction set.

60
Summary
  • Instruction complexity is just one aspect to be
    considered (trade-off between smaller code size
    and longer time to execute an instruction).
  • Design principles
  • Simplicity favors regularity
  • Smaller is faster
  • Good design demands compromise
  • Make the common case fast
  • Instruction Set Architecture (ISA) plays an
    important role in the design and is determined by
    which trade-offs are chosen.

61
Sample Question (1)
  • Which of the following should be considered in
    the data storage definition of an instruction set
    architecture (ISA)?
  • The basic unit of memory that is associated with
    an unique memory address.
  • The size of the memory space that the ISA is
    going to support.
  • The support of registers in the ISA.
  • All of the above.
  • None of the above.

Answer
62
Sample Question (2)
  • In defining the addressing modes supported by an
    instruction set architecture (ISA), which of the
    following is to be considered?
  • The expected relative usage frequencies of
    addressing modes being considered.
  • The size of displacement address defined in the
    addressing modes.
  • The size of the immediate operand defined in the
    addressing modes.
  • All of the above.
  • None of the above.

Answer
63
Sample Question (3)
  • Which of the following is true in the definition
    of instruction format of an instruction set
    architecture (ISA)?
  • All ISAs should use fixed-length instruction
    format.
  • If code size is the most important design issue,
    fixed-length instruction format should be used.
  • If performance is the most important design
    issue, variable-length instruction format should
    be used.
  • All instructions under the hybrid instruction
    format need to have the same instruction length.
  • None of the above.

Answer
64
Sample Question (4)
A certain machine has 12-bit instructions and
4-bit addresses. Some instructions have one
address and others have two. Both types of
instructions exist in the machine. Answer
questions 4 and 5.
  • What is the maximum number of instructions with
    one address?
  • 15
  • 16
  • 240
  • 256
  • None of the above.

Answer
65
Sample Question (5)
  • What is the minimum total number of instructions,
    assuming the encoding space is completely
    utilized (i.e. no more instructions can be
    encoded)?
  • 31
  • 32
  • 48
  • 256
  • None of the above.

Answer
66
Sample Question (6)
  • True/false question. For each of the following,
    indicate if it is part of ISA consideration.
  • The basic unit of memory that is associated with
    an unique memory address.
  • The size of the memory space that can be
    addressed by the ISA.
  • The communication mechanism between the register
    file and the memory system, as is seen by the
    compiler.
  • The number of register and memory operands
    allowed in an instruction.

True
True
True
True
67
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