CA Lecture 6: Digital Components

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CA Lecture 6 Digital Components

• Multiplexers/Demultiplexers
• Decoders
• Adders
• Read Textbook Appendix A.10 (excluding A10.5)

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Digital Components

• High level digital circuit designs are normally
  created using collections of logic gates referred
  to as components, rather than using individual
  logic gates.
• Levels of integration (numbers of gates) in an
  integrated circuit (IC) can roughly be considered
  as
• Small scale integration (SSI) 10 to 100 gates.
• Medium scale integration (MSI) 100 to 1000
  gates.
• Large scale integration (LSI) 1000 to 10,000
  gates.
• Very Large scale integration (VLSI)
  10,000-upward gates.
• These levels are approximate, but the
  distinctions are useful in comparing the relative
  complexity of circuits.

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Multiplexers

• A multiplexer (MUX) is a component that connects
  a number of inputs to a single output.

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Multiplexers cont.

• The output F takes on the value of the data input
  that is selected by the control lines A and B.
• E.g. if AB 00, then the value on line D0 (a 0
  or a 1) will appear at F.
• The corresponding AND-OR circuit is shown in next
  slide.

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Multiplexers Cont.
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MUX Implementation of Majority
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MUX Implementation of Majorityfunction - cont.

• Multiplexers can be used to implement Boolean
  functions. Previous slide shows an 8-to-1 MUX
  implementing the majority function.
• The data inputs are taken directly from the truth
  table for the majority function, the control
  inputs are assigned to A, B C.
• The MUX implements the function by passing a 1
  from the input of each true minterm to the output.

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MUX Implementation of Majorityfunction - cont.

• The 0 inputs mark portions of the MUX that are
  not needed in implementing the function. Thus a
  number of logic gates are not used.
• Although portions of MUXes are almost unused in
  implementing Boolean functions, multiplexers are
  popular because their generality simplifies the
  design process, and their modularity simplifies
  the implementation.

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4-to-1 MUX Implements 3-Var Function
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4-to-1 MUX Implements 3-Var Function cont.

• When AB 00, F0 regardless of whether C0 or
  C1, so a 0 is placed at the corresponding 00
  data input line on the MUX.
• When AB 01, F1 regardless of whether C0, or
  C1, so a 1 is placed at the 01 data input.

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4-to-1 MUX Implements 3-Var Function cont.

• When AB10, then FC since F is 0 when C0 and
  F1 when C1, so C is placed at the 10 input.
• When AB11, then FC, so C is placed at the 11
  input.
• Here, we can implement a 3-variable function
  using a 2-variable MUX.

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Demultiplexers

• A demultiplexer (DEMUX) is the converse of a MUX.
• A DEMUX sends its single data input D to one of
  its outputs Fi according to the setting of the
  control inputs.
• An application for a DEMUX is to send data from a
  single source to one of a number of destinations.
  E.g. from a call request button for an elevator
  to the closest elevator car.
• Not usually used in implementing boolean
  functions.

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Demultiplexers Cont.
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Demultiplexers Cont.
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Decoders

• A decoder translates a logical encoding into a
  spatial location.
• Exactly one output of a decoder is high (logical
  1) at any time, which is determined by the
  settings on the control inputs.
• A decoder may be used to control other circuits,
  and at times it may be appropriate to enable any
  of the other circuits.
• Thus it has an enable line which forces all
  outputs to 0 if a 0 is applied at its input.

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Decoders cont.

• Note that a decoder is equivalent to a DEMUX with
  an input of 1.
• One application is in translating memory
  addresses into physical locations.
• Another application is used in implementing
  Boolean functions.
• Fig. 9 below shows a 3-to-8 decoder implementing
  the majority function, where unused outputs
  remain disconnected.

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Decoders Cont.
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Decoders Cont.
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Decoders Cont.
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Programmable Logic Arrays

• A programmable logic array (PLA) is a component
  that consists of a customizable AND matrix
  followed by a customizable OR matrix.

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Programmable Logic Arrays cont.

• Next 2 slides show 3 inputs A, B, C and their
  complements available at the inputs of each of 8
  AND gates that generate 8 product terms.
• The outputs of the AND gates are available at the
  inputs of each of the OR gates that generate
  functions F0 and F1.
• A programmable fuse is placed at each crosspoint
  in the AND and OR matrices.
• The matrices are customized for specific
  functions by disabling fuses.

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Programmable Logic Arrays cont.

• When a fuse is disabled at an input to an AND
  gate, then the AND gate behaves as if the input
  is tied to a 1.
• A disabled input to an OR gate in a PLA behaves
  as if the input is tied to a 0.

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Ripple-Carry Addition, adding 2 unsigned binary
numbers
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Ripple-Carry Addition Cont.

• A full adder adds two bits and a carry and
  produces a sum and a carry.
• A half adder adds two bits and produces a sum and
  a carry.

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Ripple-Carry Addition Cont.

• Four full adders connected in a ripple-carry
  chain form a four-bit ripple-carry adder.
• Parallel computation cannot be performed.

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Ripple-Carry Addition Cont.
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Tutorial 6 questions

• Textbook appendix A.13, A.14, A.15, A.18