SPICE Model Checklist

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SPICE Model Checklist

• Kenneth Brock
• VP Marketing, Silvaco
• October 13, 2005

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FSA - TEN YEARS AND STILL GROWING

• Established in 94 to achieve a more optimal
  balance between wafer supply and demand
• 40 Charter Members
• Fabless Actel, Adaptec, Cirrus Logic, Genesis,
  Exar, NVIDIA, Level One, DSP, QLogic
• Suppliers Amkor, Chartered
• Partners Prudential
• Today FSA has almost 500 members in 21 countries
• The inaugural BOD 9
• Today 18 members fabless, IDM, Foundry, EDA
  and Back-end Supplier

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FSA MISSION
Accelerate the growth and increase the return on
invested capital of the global fabless business
model by promoting an environment for innovation.

• Provide a platform for meaningful global
  collaboration between fabless companies and their
  partners
• Identify and articulate opportunities and
  challenges to enable solutions
• Provide members with research, resources,
  publications and survey information
• Promote the fabless business model

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MS/RF SPICE Model Working Group

• Working Group Objectives
• Identify common issues shared by the foundry,
  fabless, EDA, IP and design service providers in
  the development and use of SPICE models with a
  focus on RF and Mixed-Signal
• Develop a format for SPICE model representation
  and common terminology for describing model
  contents and inputs
• Establish fabless customer requirements for MS/RF
  SPICE models
• Define SPICE model quality criteria at critical
  delivery milestones
• Streamline the SPICE model extraction and
  distribution process

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Problems with Foundry Models
Discontinuous channel conductance across bias due
to binning
Nonphysical modeling of intrinsic gain
Nonphysical modeling of normalized output
conductance
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MS/RF SPICE Model Checklist

• Objective
• Develop SPICE Model Checklist with recommended
  circuit measurements, and reports/graphs,
  delivered with each foundry model, to quantify
  and improve quality of foundry Digital, Analog,
  and RF models
• Prior Art
• FSA MOS Model Validation Procedures November
  1995
• IEEE Recommended Practices P1485 on Test
  Procedures for Micro-electronic MOSFET Circuit
  Simulator Model Validation - May 1997
• CMC Bipolar Model Standardization Proposed
  Standard Data Sets - 1999
• Benchmark tests (10) for MOSFET models developed
  at the SEMATECH Compact Model Workshop 1995

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SPICE Model Checklist

• History of PDK Working Group
• October 2002 - Founding of MS/RF Subcommittee
• October 2003 - Checklist concept is born at FSA
  Suppliers Expo for PDKs
• March 2004 - PDK Checklist Adopted by foundries
• December 2004 Foundries report full adoption
• History of SPICE Model Working Group
• August 2004 - Formed SPICE Model working group
  from PDK Checklist working group
• August 2005 Model Checklist adopted by leading
  foundries

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Working Group Members

• Foundries
• 1st Silicon AMI Semiconductor IBM Jazz
  Semiconductor Polarfab Tower Semiconductor
  Ltd. TSMC UMC and X-FAB Semiconductor Foundries
  AG
• Fabless
• Agere Systems Exar Corporation IMEC LSI Logic
  Corporation Medtronic, Inc. Mindspeed
  Technologies, Inc. PMC-Sierra, Inc. QUALCOMM
  Incorporated
• EDA Vendors
• Agilent Technologies Inc. Cadence Design
  Systems, Inc. Silvaco

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FSA MS/RF Foundry Subcommittee SPICE Model
Checklist

• What is the FSA SPICE Model Checklist?
• A three-page, FSA-endorsed document completed by
  the SPICE model developer and delivered with each
  new release of an SPICE Model
• Page 1 - foundry, process and support contact
  information and versions of foundry modeling
  documents
• Page 2 - versions of circuit simulators used to
  validate the model and a rigorous model
  classification
• Page 3 - device list with the deliverables and
  tests performed for each device.
• Serves as a combination ingredients list and
  nutrition facts label for a MS/RF SPICE model
• Helps you to better understand the source data,
  completeness and quality of the model before
  using it to design ICs or to re-extract it to fit
  into your specific product needs.

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FSA SPICE Model ChecklistServes as a Nutrition
Facts Label
Standard measured vs. simulated plots of a
typical MOSFET(ID vs. VD and its derivative RDS,
ID vs. VG and its derivate, GM)
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What is Included With the SPICE Model Checklist?

• Documents on-line at www.fsa.org
• FSA MS/RF SPICE Model Checklist (3 pages) in
  editable Word format.
• FSA MS/RF SPICE Model Checklist Users Guide (9
  pages) in pdf format
• For Fabless Companies, this document describes
  the meaning of each part of the checklist.
• For Foundries, this document describes the balls
  and strikes consistent rules for completing the
  Checklist.
• FSA MS/RF SPICE Model Checklist Definitions and
  Taxonomy (10 pages) that includes consistent
  definitions of SPICE modeling terms used in the
  other documents.

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Foundry and SupportContact Information

• Section 1 Foundry and Support Contact
  Information
• Foundry _________________________________________
  _
• Process ________________________________________
  __
• Date __________________________________________
• SPICE Model Support Contact
• Name __________________________________________
• Phone __________________________________________
• Email __________________________________________

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Section 2Foundry Modeling Documents
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Section 3Circuit Simulators
Comments
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Section 4Types of Devices Modeled
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Model Classification, Noise, Matching,
Statistical Variation, Results
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Model Identification

• Device type (list) see table
• 2. Device name (name) the foundry-defined
  unique name that invokes the schematic symbol in
  the PDK, invokes the model card in simulation,
  and the correct Pcell in layout.
• 3. Model name (name) name of the model card and
  individual model file if models are not combined
  into a single library
• Model Type (name) e.g. (BSIM3, BSIM4, EKV,
  HICUM, GP, etc. )
• 5. Version (.) ex. (3.2, 3.3, 4.4)
• 6. Model Style (same as the PDK Checklist
  column Spice Model) means that the model is one
  of the following types (Ccompact model,
  Bbehavioral, and S.SUBCKT).
• Comments
• 8. Terminals () defines the number of
  terminals on the device.

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General Model Capabilities

• 9. No of Bins () - e.g. (1, 2, 3, 4, 5 etc. for
  number of model cards to cover devices full
  operating range through automatic binning of W,
  L) measure of continuity
• 1/f Noise (list) means that the SPICE model was
  characterized for what is called 1/f, flicker, or
  low frequency noise by the following methods
  (Mmeasured, TTCAD, Eestimated, or blank if not
  included).
• HF Noise (list) means the SPICE model was
  characterized for what is called high-frequency
  or RF noise (MMeasured, TTCAD, EEstimated, or
  blank if not included) in the gigahertz range
• RF Parameters (list) means that the SPICE model
  includes any number of the following extracted RF
  parameters that were verified as per the model
  documentation (Y Y-parameters, SS-parameters,
  NNF or Noise Figure, FFT or transition
  frequency, and L NLE or non-linear effects)
• 13. High Voltage (list) means that the model
  was extracted and characterized for high voltage
  applications and includes any number of the
  following parameters that were verified as per
  the model documentation (HSelf Heating,
  BBreakdown, SSafe Operating Area, PPulsed
  Measurements).

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Statistical Model Parameters

• Statistical Model (list) summarizes the SPICE
  model included for the device (SStatistical
  Monte Carlo models have been extracted and
  verified, Mmatch models documented in Matching
  Models document, and CCorner models 4
  FF,SS,FS,SF corners are included)
• 15. Statistical Method (list) describes the
  method(s) used for the generation of statistical
  models (CPCA or primary component analysis,
  PPFA or primary factor analysis, BBPV Backward
  propagation of variance by Colin McAndrew).
  Foundries may use a combination of these methods.
• 16. Samples/Lots (/) is a two part number,
  the first part is the number of sample die that
  were used to generate the statistical models, the
  second part after the / is the total number of
  lots from which those sample die were taken.
  There is no mandated distribution of those die
  over the lots, but model users may assume that it
  is random and reflects the process distribution.

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Model Validation Metrics

• 17. Model Validation (list) means the model
  validation procedures are performed (P
  Procedure for model validation is described in
  the model documentation, R Results of the model
  validation procedure for this device are
  published in the model documentation).
• 18. Corner Validation (list) means the corner
  validation procedures are performed (P
  Procedure for corner validation is described in
  the model documentation, R Results of the
  corner validation procedure for this device are
  published in the model documentation). Corner
  validation includes tables or graphs that show
  how the statistical model corners correlate to
  the published PCM specification for the process.
• 19. Max Error (list) means the maximum error of
  Simulated vs. Measured plots (P Procedure for
  error calculation is described in the model
  documentation, R Results of the error
  calculation for this device are published in the
  model documentation). Maximum error is the
  absolute percentage or RMS percentage (as defined
  in the model documentation) that is acceptable
  for each type of plot for this device.
• 20. Number of plots () means the number of
  Simulated vs. Measured plots are included for
  this device in documentation. These plots may
  include DC plots, AC plots, RF plots, S
  parameter, Y parameter, W elements, and ring
  oscillator performance.

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Section 5Active Device Specific Parameters
Device Specific Extraction and Model Parameters
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Section 6Passive Device Specific Parameters
Device Specific Extraction and Model Parameters
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FSA MS/RF SubcommitteeSPICE Model Checklist

• What it is
• Enhances communication within MS/RF supply chain
  with a common language
• Tracks versions of foundry documents, EDA tools,
  SPICE models
• Lists contents of the model library
• Serves as a nutrition facts label for foundry
  supplied SPICE models, showing both the good and
  bad characteristics in a consistent, easy to read
  format.
• What it is not
• Marketing brochure
• Process Spec Sheet
• Device Spec sheet

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Benefits for Fabless, Fablite, Foundry, and EDA
Vendors

• Fabless and Fablite
• Consistent documentation and version control
• Easily compare completeness and quality of model
• Quickly determine if model needs enhancement
• Foundry
• Centralized documentation and version control
• Saves customer support resources common
  questions
• Shortens initial engagement timeclarity,
  confidence, trust
• EDA Vendor
• Easier to support customers with model, circuit,
  simulator issues
• Easier to support foundry partners
• Easier to integrate models into PDKs

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Conclusions and Next Steps

• Conclusions
• The success of the FSA MS/RF SPICE Model
  Checklist depends on good models being
  standardized by the CMC. We follow your
  leadership and make the best of it.
• Next Steps
• Next meeting on Tuesday, November 8, 2005 at
  900AM at Silvaco in Santa Clara, CA
• Agenda includes discussing problems for foundries
  implementing checklist by end of 2005
• Phase 2 will focus on model validation suites,
  statistical model validation suites
• Current MOS guidelines in Checklist to be further
  developed for MOS-RF, BJT, and passives in select
  regions (saturation, linear, sub-threshold) and
  applications (digital, analog/mixed mode, high
  voltage and RF)