Data rate reduction in ALICE

1
Data rate reduction inALICE
2
Data volume and event rate
bandwidth
TPC detector data volume 300 Mbyte/event data
rate 200 Hz
60 Gbyte/sec
front-end electronics
15 Gbyte/sec
Level-3 system
lt 2 Gbyte/sec
DAQ event building
lt 1.2 Gbyte/sec
permanent storage system
3
Data rate reduction

• Volume reduction
• regions-of-interest and partial readout
• data compression
• entropy coder
• vector quantization
• TPC-data modeling
• Rate reduction
• (sub)-event reconstruction and event rejection
  before event building

4
Regions-of-interest and partial readout (1)

• Selection of TPC sector and ?-slice based on TRD
  track candidate

• Momentum filter for D0 decay tracks based on TPC
  tracking

5
Regions-of-interest and partial readout (2)

• Momentum filter for D0 decay tracks based on TPC
  tracking
• pT gt 0.8 GeV/c vs. all pT

6
Data compressionEntropy coder
Probability distribution of 8-bit TPC data

• Variable Length Coding
• short codes for long codes for
• frequent values infrequent values
• Results
• NA49 compressed event size 72
• ALICE 65
• (Arne Wiebalck, diploma thesis, Heidelberg)

7
Data compression TPC - RCU

• TPC front-end electronics system architecture and
  readout controller unit.

• Pipelined Huffman Encoding Unit, implemented in a
  Xilinx Virtex 50 chip

T. Jahnke, S. Schoessel and K. Sulimma, EDA
group, Department of Computer Science, University
of Frankfurt
8
Data compressionVector quantization

• Sequence of ADC-values on a pad vector

compare
code book

• Vector quantization transformation of
  vectors into codebook entries
• Quantization error

Results NA49 compressed event size 29
ALICE 48-64 (Arne Wiebalck, diploma
thesis, Heidelberg)
9
Data compression TPC-data modeling

• Fast local pattern recognition
  

simple local track model (e.g. helix)
track parameters

• Track and cluster modeling

comparison to raw data
local track parameters
analytical cluster model
quantization of deviations from track and
cluster model
Result NA49 compressed event size 7
10
Event rejection
L0
TRD
Global
L0
Trigger
Trigger
2 kHz
L1
Readout
L1
Readout
Other Trigger
L1
other detectors
TPC
Detectors
,
L0pretrig.
L2
accept
L2
(216 Links, 83 MB/
evt
)
TRD
Zero
suppressed

-
e
e
tracks
TPC
data
Sector
parallel
Select
Detector raw data readout for debugging
HLT
Event sizes and number of links TPC only
regions
of
seeds
interest
Tracking
of
On
-
line
data reduction

-
e
e
candidates
(
tracking
,
reconstruction
,
inside
TPC
partial
readout
,
compression
)
enable
Verify
e

e
-
hypothesis
Track
segments
e

e
-
tracks
Reject
and
space points
plus
ROIs
event
Time, causality
Binary loss less data compression
(RLE, Huffman, LZW, etc.)
0.5
-
2 MB/
evt
4
-
40 MB/
evt
45
MB/
evt
DAQ
11
Fast pattern recognition

• Essential part of HLT system
• crude complete event reconstruction
• ? monitoring, event rejection
• redundant local tracklet finder for cluster
  evaluation and data modeling ? efficient data
  compression
• selection of (?,?,pT)-slices
• ? ROI
• momentum filter
• ? ROI
• high precision tracking for selected track
  candidates
• event rejection

12
Requirements on the TPC-RORC design concerning
HLT tasks

• Transparent mode
• transfering raw data to DAQ
• Processing mode
• Huffman decoding
• unpacking
• 10-to-8 bit conversion
• pattern recognition
• cluster finder
• Hough transformation tracker

13
TPC PCI-RORC

• Simple PCI-RORC

• HLT TPC PCI-RORC
• backwards compatibility
• fully programmable
• ? FPGA coprocessor

FPGA Coprocessor
DIU
PCI bridge
Glue logic
interface
DIU card
SRAM
PCI bus
14
Preprocessing per sector
RCU
raw data, 10bit dynamic range, zero
suppressed Huffman encoding (and vector
quantization)
detector front-end electronics
Huffman decoding, unpacking, 10-to-8 bit
conversion
fast cluster finder simple unfolding, flagging
of overlapping clusters
RORC
fast track finder initialization (e.g. Hough
transform)
cluster list
fast vertex finder
Hough histograms Peakfinder
receiver node
global node
vertex position
raw data
15
FPGA coprocessorcluster finder

• Fast cluster finder
• up to 32 padrows per RORC
• up to 141 pads/row and up to 512 timebins/pad
• internal RAM 2x512x8bit
• timing (in clock cycles, e.g. 5 nsec)1
  (cluster-timebins per pad) / 2 clusters
• ? outer padrow 150 nsec/pad, 21 ?sec/row

• centroid calculation pipelined array multiplier

1. Timing estimates by K. Sulimma, EDA group,
Department of Computer Science, University of
Frankfurt
16
FPGA coprocessorHough transformation

• Fast track finder Hough transformations2
• (row,pad,time)-to-(2/R,?,?) transformation
• (n-pixel)-to-(circle-parameter) transformation
• feature extraction local peak finding in
  parameter space

2. E.g. see Pattern Recognition Algorithms on
FPGAs and CPUs for the ATLAS LVL2 Trigger,
C. Hinkelbein et at., IEEE Trans. Nucl. Sci. 47
(2000) 362.
17
Processing per sector
raw data, 8bit dynamic range, decoded and unpacked
vertex position, cluster list
slicing of padrow-pad-time space into sheets of
pseudo-rapidity, subdiving each sheet into
overlapping patches
RORC
sub-volumes in r,?,?
fast track finder B 1. Hough transformation
fast track finder A track follower
fast track finder B 2. Hough maxima finder
3. tracklett verification
track segments
receiver node
cluster deconvolution and fitting
updated vertex position updated cluster
list, track segment list
18
Hough transform (1)

• Data flow

19
Hough transform (2)

• ?-slices

20
Hough transform (3)

• Transformation and maxima search

21
FPGA coprocessorImplementation of Hough
transform
22
FPGA coprocessorprototype
FPGA Coprocessor
PCI bridge
Glue logic
FEP
RAM
SRAM
PCI bus
DIU
SIU
interface
interface
DIU card
RCU
SIU card

• FPGA candidates
• Altera Excalibur (256 kbyte SRAM)
• Xilinx Virtex II (3.9 Mbit dual port SRAM 1.9
  Mbit distributed SRAM, 420 MHz)
• external high-speed SRAM