Title: High Speed Logic : Chapter2 High speed properties of logic circuits
1High Speed Logic Chapter2High speed properties
of logic circuits
- Motivation To study the important
characteristics of the switching elements in
digital circuits
2Chapter 2 High speed properties of logic gates
Contents
- 2.1 Power
- Quiescent and Active
- 2.2 Speed
- large dI/dt problem, ground bounce
- 2.4 Packaging
- 2.5 Temperature characteristics
- refhttp//www-us2.semiconductors.philips.com/pip/
74HC1G00GWdatasheet
32.1 Power
- The story of power
- A portable computer can run for 3 hours before it
needs recharge another can run for 10 hours.
Which one will you choose? - It is all about power. It is becoming important
as smaller computers (palm size computers) are
getting more and more popular.
4To learn about
- Quiescent (output no change) or active power
(output changing) - power calculation (Quiescent or active) at
different stages inside a logic circuit. - input power
- internal dissipation
- drive circuit dissipation
- output power
- Detailed power calculation is very complicated,
here we only introduce the important points
5Which part consumes more power?
Ref1
6Four ways to consume powerThey can be active or
quiescent
worksheet 2.1
Output power stage i-1
Stage i-1
Input power i
Stage i
Internal i
Drive circuit i
Load output power i
Stage i1
7Basic rules for Quiescent and Active power
worksheet 2.2
- Quiescent power -- power to hold a circuit in one
logic state. - Active powercycle frequency excess power used
per cycle. - common causes of active power dissipation
- load capacitance and overlapping bias current
8(1)Input power (relatively small, E.g.
CMOS-74HCT00, at 10MHz, takes 9mW, table 2.1 1)
- Used for bias and activate the input circuit.
- Quiescent power equal to input current(IIL)
power supply voltage. - Active power depends on capacitance (CIN) of the
input, see load power calculation. - CIN and IIL can be found in data books.
- Exercise Check CIN and IIL of XC95108 from
http//www.xilinx.com/ - http//www.xilinx.com/support/documentation/data_s
heets/ds069.pdf
9(2)Internal dissipation (relatively small)
- Used to bias and switch nodes internal to a logic
gate including both active and quiescent. - CMOS internal dissipation CPDV2F
- CPDequivalent power dissipation capacitance, see
- http//www-us2.semiconductors.philips.com/pip/74H
C1G00GWdatasheet - E.g. CPD 19pF for Philips 74HC1G00
10(3)Drive circuit power (large) (4)output
(large)
- Most power consumption goes to the output circuit
especially it is connected to a capacitive load.
11Drive circuit quiescent power
- Power for keeping the output at either 1 or 0.
12Drive circuit quiescent powerfor CMOS Totem-pole
output low
- Example for CMOS
- first find the internal Resistors
- Typical (average) values, at
- VOL0.15V, (IOL(sink) 4mA),
- therefore Rlow0.15/0.00437 ?
Vcc4.5V
Rhigh
Low
Isink
Rlow
13Drive circuit quiescent powerfor CMOS Totem-pole
output high
- Example for CMOS
- Typical (average) values
- VOH4.32V, (IOH(source) -4mA)
- Rhigh(4.5-4.32)/0.004
- 0.18/0.00445 ?
- Pquiescent Rlow(Isink)2 Rhigh(Isource ) 2/2
Vcc4.5V
Rhigh
High
Isource
Rlow
worksheet 2.3
14Drive circuit active power
- Power for switch the output between 0 and 1 at a
frequency
15Drive circuit Active power CMOS Totem-pole output
on capacitive load
Draw current flow at each time interval
Switch A
Close open
Vcc
Plot Vout
Switch B
Close open
Switch A
t1
t2
Rcharge
t4
t3
t5
t6
t7
Capacitor Load
Switch B
Rdischarge
Vout
16Drive circuit Active power CMOS Totem-pole output
on capacitive load (Largest)
- At t1, A closes, charge capacitance load Rcharge.
- At t2, B closes, discharge capacitor thru
Rdischarge. - Energy_per_cycle2 ? (1/2) ? C ? Vcc2C? Vcc2
- (see appendix)
- Ccapacitance, Vcccharge voltage
- Active power F ? C ? Vcc2
- Energy dissipated at Rcharge and Rdischarge but
not in the capacitor. - Exercise Why the energy does not depend on the
resistors?
Exercise
17Examples
- Actual examples and to show power dissipation
calculations - A Tour of the 74HC00 data sheet
- http//www-us2.semiconductors.philips.com/pip/74HC
1G00GWdatasheet - see page2 CPD and dynamic power calculations
- page5 typical high low /input output voltages
VIL,VIH, VOL,VOH. - Use current calculation to find fan out.
18More example on XC95108
- XC95108
- http//www.xilinx.com/partinfo/95108.pdf
- Use current calculation to find fan out.
19Fan-in and Fan-out
- The number of inputs of a device fan-in.
- E.g. fan-in of this and gate is 4.
- The number of inputs that an output can drive is
fan-out. For example, - fan-in of the AND gate is 2
- fan-out of the AND gate is 5
20Temptation to drive more inputs
- CMOS-XC95108, output current 24mA (for around 50
pins ), input current (IIL, IIH)10uA, so fan-out
can be high. So what is the actual fan-out? - But Dont drive too many outputs,
- because it
- (problem 1) runs slower
- (problem 2) consumes more power
worksheet 2.4
We will show you why
21Example of a shared memory bus -- power speed,
Fig2.81
One output is driving 20 inputs Fanout20
22Example of a shared memory bus -- power speed
calculations
worksheet 2.5
- Shared memory
- 20 CPUs connected to a 8-bit wide RAM
- One CMOS output is driving 20 inputs.
- Each input capacitance is 10pF. So each output is
driving 20x10pF capacitance. - Traces (2pF/in.) are 10 in. long
20(inputs) 1(trace) capacitors
cap. of the Trace
20 inputs
23Find total capacitive load seen by an output
- Approximation all capacitive loads are in
parallel - Total load capacitance
- 20 x each input cap. trace cap.
- (10pF/driver )x20(2pF/in.)x 10 in
- 220pF
1 cap. Of The trace
20 inputs
20 capacitors
24(Problem 1) Rise/Fall time is too large for
large capacitive loads
- FR-4 board160ps/in, so delay for trace is 1.6ns
- high side output resistance110 Ohms.
- RC rise time constant (0-63 rise) TRC110
220pF24ns - 10-gt90 rise time 2.2 TRC 53ns (prove it!)
- So total time delay is (531.6)ns, the reason is
the capacitance of the load is too large. - High speed CMOS rise time is typically below
10ns, but now it is 55ns !!. Think about it.
worksheet 2.6
25Rise/Fall time is too long, clock frequency is
slowed down
1 cycle T (5510)x2130ns F1/T7.7MHz (slow)
Some margin for the flat top 10ns
Rise time 55ns
Fall time 55ns
Some margin for the flat bottom 10ns
26(Problem 2) Power calculation per output,
PowerFfreqCcapV2
- Vc5.5V, C220pF
- Fclock16MHz, Fdata(max)8MHz
- PactiveFCV2(8x106)(220x10-12)(5.5)20.053W
- For 8 outputs (8-bit output) 8 Pactive 0424W
- 8PQuiscent 8 5.5 (6mA/driver)0.264W
- Conclusion It is too much for an 8-driver chip.
- Exercise Calculate power for Fclock8MHz.
worksheet 2.7
27Delays and switching time
28Delays and switching time
- Delay is how much time needed for the output to
response to the input. - Switching time refers to the time it switches
from one state to another rise or fall time of
the circuit. - They are not the same.
29Propagation delay switching time They are not
the same!!
- Propagation delay, Time between logic switching
at A and B. (The faster the better) - Output switching T10-90 at output. (The slower
the better) (see Fig.2.13 of 1.)
302.2 Speed and its problems
- It tells you how fast a computer can run.
31The horror of large dI/dt
- Since ?V -L dI/dt , Linductance.
- Since the traces are inductive, Large dI/dt will
create huge noise voltage ?V in the circuit.
dI/dt
?V
Large dI/dt creates large voltage ?V here
32Speed dI/dt problem
- Logic families having minimum switch times much
faster than the propagation delay suffer an
unnecessary penalty in system design. Large dI/dt
creates problems. - Given two families with identical propagation
delay statistics, the family with the slowest
output switching time will be cheaper and easier
to run. - Some logic families (ECL, MECL) have circuits to
limit switching time.
33Speed dV/dt problems
- Circuit response lower than Fknee may distort
signal, circuit response higher than Fknee is not
important in our design. - Shorter Tr (switch time) results in higher Fknee.
So unnecessary short Tr is a problem. - So shorter Tr will not work in poorly designed
circuits. - Shorter Tr will give larger dI/dt, which will
cause ground bounce. (will be discussed later)
34How to find dI/dt from dV/dt
- dI/dt creates problems.
- Since dV/dt is easier to measure, so we try to
find dI/dt from ?V (output voltage
change),Tr(rise time) and C(load capacitance). - We will show that
- max(dI/dt) 1.52 ?V C/(Tr)2
35Fig.2.14 of 1
36Show two important relations
- max(dV/dt) ?V/Tr
- max(d2V/dt2) 1.52C?V/(Tr)2
worksheet 2.8
37Effect of dI/dt, by dV/dt. dI/dt is difficult
to measuredV/dt is easier to measure
Very big
38Effect of dI/dt, by dV/dt. dI/dt is difficult
to measuredV/dt is easier to measure
Very big more significant
39Max(dIcapacitor/dt) ? 1/T10-902 Shorter Tr will
give larger dI/dt, which will cause ground
bounce. (talk later)
- Where does this formula come from?
402.3 Noise margin
- It tells you how much noise it can tolerate.
- We do need this information to explain ground
bounce.
41Noise Margins -- digital logic gates are not
perfect
- Noise margin is the maximum amplitude of the
noise pulse that will not change the state of the
driven stage. - A measure for the resistance of noise in the
circuit. - Circuit A -----------gtCircuit B
- (VOH min,VOL max) (VIH min,VIL max)
42Noise margins
- High noise margin VOH min - VIH min
- Low noise margin VIL max- VOL max
- Noise marginmin(High noise margin, Low noise
margin)
VIH max
VOH max
High noise margin
VOH min
VIH min
Low noise margin
VOL max
VIL max
VOL min
VIL min
43Example for a TTL gate
- High noise margin VOH min - VIH min 2.4
-2.00.4V - Low noise margin VIL max- VOL max 0.8-0.40.4V
- Noise marginmin(High noise margin, Low noise
margin)0.4V
VIH max
VOH max
High noise margin
VOH min 2.4
VIH min 2.0
Low noise margin
VOL max
VIL max 0.8
VOL min 0.4
VIL min
44Classroom work
Also see tutorial 2.5
- Find the overall noise margin of a high speed
CMOS 74HC1G gate when operating at Vcc0.45V (See
next slide) - Repeat the calculation when Vcc6V.
45From http//www-us2.semiconductors.philips.com/p
ip/74HC1G00GWdatasheet
46ANS
- Use Vcc4.5
- VOH min 4.4V , VIH min 3.15V
- VIL max1.35V , VOL max 0.1V
- High noise margin VOH min - VIH min 4.4 -
3.151.25V - Low noise margin VIL max-VOL max1.35-0.11.25V
- Overall margin
- min(High noise margin, Low noise margi)n1.25V
472.4 The problem of ground bounce
- A problem because of
- high switching speed (short Tr)
- inductance at ground wire and
- capacitive load at the next input stage.
48Why do we dislike large dI/dt?Ground bounce
double clocking
Vcc
- Capacitor load, from H to L, discharge of C
passes through LGND creates a large VGND causing
ground bounce.
Idischarge
gate
Input
Capacitive load C
LGND
VGND
49Fig. 2.17 1 Ground bounce double clocking
50Example of Ground bounce and double clocking
- Figure 2.17 of 1, double clocking
- At time A, a rising clock edge latches data into
the flip-flop and after 3ns it appears at the
outputs. - At B, 00 is clocked into the flip-flop.
- At C, data input changed to XX.
- At D, Q outputs change from FF to 00, This
change creates a large VGND (ground bounce). - Clock-VGND clocks XX into the flip-flop.
51Solution to double clocking problem
- Double clocking happens on DIP flip-flop packages
with fast output and capacitor load. - Surface-mounted packages with their shorter pins
are less susceptible to this problem. - Solution Provide multiple power pins (XILINX
chips) to lower dIGND/dt. - Special packages to reduce lead inductance
- Wire bond, Tap Automated Bonding (TAB), Flip-chip.
522.5 packaging
- Bad (cheap, e.g. DIP) packaging give more
inductance and capacitance to leads, occupy more
space, which are all bad news for circuit
designers. - Better packing methods are wire-bond, tape bond,
flip chips etc. - Check the packages provided for Xilinx
http//www.xilinx.com/
53http//en.wikipedia.org/wiki/Wire_bonding
Bounding types Fig.2.20 1
http//en.wikipedia.org/wiki/Flip_chip
54Surface mounted technology (SMT)
- reduce inductance, mutual capacitance and
manufacturing cost
http//en.wikipedia.org/wiki/Surface-mount_technol
ogy
552.3 Packages and their lead inductance,
capacitance
- 14-pin plastic (DIP) 8nH, 4pF
- 68-pin plastic (DIP) 35nH, 7pF
- 68-pin surface mount PLCC 7nH
- wire bounded to hybrid substrate 1nH, 1pF
- Solder bump to hybrid substrate 0.1nH,0.5pF
56LGA775(LGA) Flip-chip land grid array
- The socket contacts 1.09mmx1.17 mm pitch (X by Y)
in a 33x30 grid array with 15x14 grid
depopulation in the center of the array..
http//en.wikipedia.org/wiki/Socket_775
"www.intel.com/Assets/PDF/designguide/302666.pdf "
57Cross talk at leads
- Designers nightmare and how to handle it.
58Lead capacitance
- Stray capacitance between pins attracts noise.
- Cross-talkCMR(input R of receiver) /Tr
- (Fig. at Next slide) It is still OK, if the input
has a parallel small R of 75?. Cross-talk3. - If R2 10K, cross-talk800.
- Rule Add capacitors connected to large pull-up
resistors for reducing cross-talk.
59Cross-talkR2CM/T10-90, 4pF37.5?/5ns0.03(3),
still OK.But when T10-90 1 ns, cross-talk15
!!
See tutorial 2.7
60For high pull up Resistors, add capacitors to
reduce cross-talk. Cross-talkCM/C1 (why?)Hints
impedance of C1/j(2?Frequency)C
Class Exercise, What is the conclsuion?
612.6 heat transfer
http//en.wikipedia.org/wiki/Heat_sink
http//www.wakefield.com/default.htm
622.4 Heat transfer, E.g. at 0.5W dissipation,
lower ambient temperature will lower internal
temperature
- Higher internal temperature results in
- higher power dissipation and higher failure rate
- Add heat-sink or fan to lower temperature.
Tjunction
63Thermal resistance
http//en.wikipedia.org/wiki/Computer_cooling
Manufactures usually quote heat-sink air-flow
spec. at 400ft/min with good airflow design.
The fan in you PC gives about 150 ft/min.
64Exercise Thermal resistance of a 16-pin dual DIP
Package
classroom exercise
- ?JC Junction to case 34oC/W
- Case 1 (Still Air) ?CA-stillAir Case to Ambient
80oC/W - Case 2 (400 ft/min, heat sink) ?CA-400ft/minAir
Flow Case to Ambient 35oC/W - Calculate internal temperatures for both cases,
if internal power dissipation is 0.5W, ambient
temp is 20oC for both cases.
65Ans
- Case 1
- Tjunction120(3480)0.5
- 205777oC
- Case2
- Tjunction2 20(3435)0.5
- 20690.5
- 2034.5
- 54.5oC
66Appendix
VR Vcc
Rcharge
VCVcc(1-e-t/RC)
- When charging the capacitor
- EchargEdischarg
- (1/2)C(Vcc)2
- Energy_per_cycle(T)
- EchargEdischarg
- 2 ? (1/2) ? C ? Vcc2C? Vcc2
67Reference
- 1 High-Speed Digital Design A Handbook of
Black Magic by Howard W. Johnson and Martin
Graham Prentice Hall.