Leakage Power Reduction of Embedded Memories on FPGAs through Location Assignment

1
Leakage Power Reduction of Embedded Memories on
FPGAs through Location Assignment

• Yan Meng, Tim Sherwood, and Ryan Kastner
• University of California, Santa Barbara
• Department of Electrical Computer Engineering
• ExPRESS Group http//express.ece.ucsb.edu

2
Outline

• Motivation
• The leakage problem of embedded memories on FPGAs
  is of growing importance
• Synthesis techniques for leakage power
  optimization of embedded memories
• Conclusions

3
Motivation

• FPGAs are attractive options
• High processing power, flexibility,
  reconfigurability
• Power is becoming critical
• Why worry about power?
• Heat dissipation, portability
• Where does power go in CMOS?
• Dynamic power consumption
• Switching power due to charging and discharging
  load capacitors
• Short circuit currents between supply rails when
  both transistors are on during switching
• Leakage power consumption

4
Technology Scaling and Leakage Power Dissipation

• Leakage is dominating over dynamic power as
  technology scales down (improving speed,
  transistor density and functionality)

5
On-chip Memory Leakage Control

• Why control leakage through on-chip memory?
• Huge portion of chip area
• Leakage is proportional to the number of
  transistors
• Major source of leakage consumption Roy01, Hu01,
  Flautner02,Mudge04
• Caches on microprocessors
• 50 2005 ITRS 02
• Dynamic reshuffling due to cache replacement
  policies
• Cache hierarchy with data replication
• Memories on FPGAs
• Configuration SRAMs not on critical paths, high
  Vth
• Embedded memories
• Accesses are usually statically scheduled
• Not necessary a part of memory hierarchy with
  inclusion

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Leakage Power Optimization of Embedded Memories
on FPGAs
Embedded memory bits/logic cells gt 20x
20x

• Leakage problem of embedded memories isof
  growing importance

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Motivating Example

• Temporal information
• Spatial information

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Outline

• Motivation
• Synthesis techniques for leakage power
  optimization of embedded memories
• Temporal
• Temporal spatial
• Conclusions

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Temporal Information

• Precedence order between variables
• Saving power on variables
• Keep frequently accessed lines active to ensure
  high performance
• Turn off lines that are not used for a long time
• Use low supply voltage to save power for the rest
• Using the generalized model to calculate maximal
  leakage power savings for variables Meng HPCA05

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Definitions Intervals

• Live interval
• time between two successive accesses to the same
  variable v within a memory entry

• Dead interval
• time before the first access or after the last
  access to a variable

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Definitions Operating Modes

• Active mode
• Power on the whole line
• No power saving

• Sleep mode Roy01, Hu01
• Sleep/turn off transistors
• Lose data

• Drowsy mode Flautner02,Mudge04
• Use low supply voltage to save power when it is
  not needed
• Preserve data for fast reaccess
• Wake up to the high voltage and return data

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Choosing Operating Modes

• Active mode
• Sleep mode
• Drowsy mode

Ii
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Inflection Points

• Which mode to apply on each interval?
• Active-drowsy inflection point a
• The least amount of time drowsy mode needs to
  save energy
• Sleep-drowsy inflection point b
• The time where sleep and drowsy modes consume the
  same amount of energy

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Selecting Operating Modes with Inflection Points
Active Interval
Active Mode
0ltIa
Drowsy Interval
Drowsy Mode
I?
I
altIb
Igtb
Sleep Interval
Sleep Mode
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Optimal Leakage Management Policy

• Oracle knowledge of all interval lengths based on
  static scheduling
• Applying the appropriate operating mode on each
  variable interval
• Obtaining maximal leakage power saving
• Formal proof of the optimality Meng HPCA05

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Outline

• Motivation
• Synthesis for leakage power optimization of
  embedded memories
• Temporal
• Temporal spatial
• Conclusions

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Spatial Information

• Spatial layout of data leads to different
  potentials of power savings

One variable per entry
Minimal number of entries
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Memory Leakage Optimization Techniques
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Location Assignment Schemes (I)

• The state of the art no leakage control

Full-active
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Location Assignment Schemes (II)

• Turning off the unused part

Used-active
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Location Assignment Schemes (III)

• Packing variables into the minimal number of
  entries and turning off the rest

Min-entry
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Location Assignment Schemes (IV)

• Min entry sleep dead intervals

Sleep-dead
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Location Assignment Schemes (V)

• Min entry sleep dead drowsy long

Drowsy-long
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Extended DAG Modeling
4 entries
I1
I3
Spatial information

• Temporal information

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Path-place Algorithm

• Greedily covering DAG with N node-disjoint
  paths. The length of a path indicates the power
  saving of a memory entry.
• First sort all vertices in topological order
• A vertex is covered each time to calculate the
  longest path reaching it, iff not adjacent to
  other nodes
• Sum the weights of the final level vertices,
  edges,
• and virtual edges from start to end if k lt N
• Complexity O((ne)N)

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Location Assignment Schemes (VI)

• Data layout with leakage awareness
• Power savings on unused entries, dead and live
  intervals

Path-place
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Location Assignment Schemes
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Embedded Memory Leakage-aware Design Flow

• Exploring temporal and spatial information
• Path traversal and location assignment
• Introduced for deciding the best data layout
  within embedded memory to achieve the maximal
  leakage saving

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Radix-2 FFT Example
Scheduling
Path traversal
Location assignment
Compilation
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Empirical Study

• Experimental setup
• Simulation of a configurable double-port
  synchronous RAM with 18K-bits
• Read/write ports both ports can read the same
  memory cell simultaneously, but cant write to
  the same location (no write conflict).
• Configurable 1-bit, 2-bit, 4-bit, 9-bit, or
  18-bit
• eCACTI Dutt04 modeling transistor leakage
• DSP benchmarks dft, idft, fft-2, fft-4, filter,
  mp

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Comparing Different Schemes
95
76
37
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Conclusions

• Leakage is dominating dynamic power as
  technology scaling trends hold
• Leakage problem of embedded memories is of
  growing importance
• Explored temporal and spatial information for
  optimizing leakage power, achieving significant
  leakage saving 95

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Backup
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Multimedia, Internet, Cellular Telephony
Wont work The machine is too hot. The battery
is too heavy.
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Power Optimization Techniques
Power Design Time Non-active modules Run time
Dynamic Reduced Vdd Logic synthesis Pin ordering Transistor sizing Multi-Vdd islands Path balancing Tradeoff area for power Clock/power gating DVS DFS (based on workload)
Leakage Multi-Vth MTCMOS (critical/non-critical paths) Sleep transistors Multi-Vdd Variable Vth Variable Vth
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Saving Leakage Power without Performance
Degradation

• Deriving the interval lengths with static
  scheduling
• Scheduling any needed datajust before it is
  needed
• Avoiding any performance impact

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The Generalized Model

• Parameterized model
• Inputs
• Wake-up latencies
• Interval distribution
• Leakage power of each state
• Transition energy between states
• Output
• Maximal power saving

P(Active)
P(Sleep)
Meng HPCA05
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Example of path-place
start
e1
e4
E1
I1 w1
E2
I4 w4
e2
E3
I2 w2
TopList I4, I1, I2, I3
e5
e3
E8
E7
E6
E4
E5
I3 w3
e6
end
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Outline

• Motivation
• Synthesis for leakage power optimization of
  embedded memories
• Temporal
• Temporal spatial
• Conclusions