A Visual Language for Describing Instruction Sets and Generating Decoders

1
A Visual Language for Describing Instruction Sets
and Generating Decoders

• Trevor Meyerowitz, Jonathan Sprinkle, Alberto
  Sangiovanni-Vincentelli
• E-mail tcm, sprinkle, alberto_at_eecs.berkeley.edu
  
• OOPSLA Workshop On Domain Specific Modeling
• October 24th, 2004

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Modeling Overview

• Goals
• Accurate software performance modeling for a
  variety of processors and instruction sets.
• Reuse and retarget trace-driven
  microarchitectural models
• Automate the retargeting
• Retargeting Requires
• Building Cross Compiler
• Modifying the ISS to generate traces
• Creating a trace-reader for the
  microarchitectural model

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A Sample Instruction Set (ARM)
C Code Assembly Code Instruction Word ( binary)
x x 1 add r1, r1, 1 11110010100000010001000000000001
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ISA_ML Overview

• Main Parts
• A Visual Instruction Set Description Language
• Used to describe the encoding and operand usage
  of instructions
• Written using GME, a UML-based environment for
  constructing domain specific modeling
  environments
• Generates a C-based disassembler and
  trace-interface code for the given model ISA
  description
• Key Features
• Two high level models
• ISA State Register Files, Memories, Program
  Counter, etc.
• Instructions Encoding and operand fields of each
  instruction
• Intuitive Visual Interface
• Leverages Hierarchy Compact Representation
• Extensive Error Checking
• Easier to Retarget to Output Other Formats (e.g.
  verilog, nML, etc)

GME website http//www.isis.vanderbilt.edu/proje
cts/gme/
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Outline

• Background
• Paradigm and Semantics
• ISA State
• Instructions
• Instructions and Operands
• Sample Instruction Group
• Language Rules
• Interpreter Implementation
• Final Words

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ISA_ML Paradigm
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ISA State

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Instructions and Operands
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Sample Instructions Base Instruction
Instruction 01 2...5 69 10..13 14..17 18..21 22..23 24..27 28..31
Arith Base 11 xxxx Rm Rn xxxx xxxx xx xxxx Rd
Add 11 0111 Rm Rn xxxx xxxx xx config Rd
Subtract 11 0001 Rm Rn xxxx xxxx 00 config Rd
MAC 11 0011 Rm Rn Rmac xxxx xx xxxx Rd
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Sample Instructions MAC
Multiply Accumulate
Instruction 01 2...5 69 10..13 14..17 18..21 22..23 24..27 28..31
Arith Base 11 xxxx Rm Rn xxxx xxxx xx xxxx Rd
Add 11 0111 Rm Rn xxxx xxxx xx config Rd
Subtract 11 0001 Rm Rn xxxx xxxx 00 config Rd
MAC 11 0011 Rm Rn Rmac xxxx xx xxxx Rd
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Language Rules

• Enforced by Constraints (via OCL)
• The operands of an instruction must have unique
  names.
• Each instruction has a unique name, and uniquely
  named operands
• Each reference operand must be non-null
• Each operand has at most one incoming and one
  outgoing connection
• Enforced at Interpreter Run-time
• Fully deterministic ordering within an
  instruction.
• All operands must be connected in directed
  acyclic line segments.
• All actual instructions must have the same
  bit-width
• Only instances and subtypes of base instructions
  are allowed in other instructions
• The operands of an instruction must be consistent
  with the encoding of the instruction (i.e. their
  bit-field sizes must be less than or equal to the
  number of dont cares (xs) in the instructions
  bit field)

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Outline

• Background
• Paradigm and Semantics
• Interpreter Implementation
• Interpreter Flow
• Generated Files
• Interpreter Results
• Final Words

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Interpreter Flow

• Instruction Processing/Parsing
• Get encodings (base/actual instructions)
• Check language rules
• Create internal representation from network
• Consistency Check
• No actual instruction encodings overlap
• bit-by-bit comparison of the encoded instructions
• Data Structure Synthesis
• Instruction data structures/unions
• Decoding masks/signatures
• Disassembler and Trace Reader Base Code

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Example Generated Files
//bitfield // 110011xxxxxxxxxxxxxxxxxxxxxxxxxx typedef struct _MAC_struct unsigned dummy0 2 unsigned BeginConstants 4 // Pos29 unsigned Rm 4 // Pos25 unsigned Rn 4 // Pos21 unsigned Rmac 4 // Pos17 unsigned dummy1 10 unsigned Rd 4 // Pos3 MAC_struct define MAC_MASK 0xfc000000 define MAC_SIG 0xcc000000
MAC Structure, Mask, and Signature
// the union of ALL of the // instruction field structures typedef union _insts unknowni_struct unknown_inst MAC_struct MAC_inst SUB_struct SUB_inst ADD_struct ADD_inst insts
Union for Decoding Instructions
Note The interpreter also generates specific
files for Disassembling and Trace Interfacing.
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ISA_ML Results
MIPS Integer Subset PowerPC Integer Subset ARM (approximate)
Base Instructions 11 11 6
Actual Instructions 55 91 26
Illegal Instructions 0 0 5
Hours to Enter (appox.) 8 6 6
Header File ( lines) 1357 2134 759
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Final Words

• Conclusions
• Succinct DSME for describing ISAs and their
  encodings
• Flexible and intuitive syntax and semantics
• Extensive static run-time error checking
• Synthesis of disassembler and trace interface
  code
• GME has enabled rapid design of ISA_ML
• SW-Engineering Framework
• Extensive Infrastructure Support (Language, GUI,
  Interpreter)
• Potential Improvements
• More customizable types input methods
• API support to ease code generation (for C/C,
  etc).
• Future Work
• Expansion of Language and Features
• E.g. Richer operands, multiple bit-length
  instructions
• Addition of execution semantics
• Connection to other targets
• E.g. metropolis, architecture description
  languages, hardware description languages

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Thank You!!!
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Dual Process ARM Microarchitectural Models

• Models
• Pipeline delays
• Result and Issue delays
• Doesnt Model
• Interrupts, Exceptions, Non-Ideal Memory
• Value dependent execution times (e.g.
  multiplication)
• Stalling Behavior
• Operation Stall
• Fetch stall until notified
• Execute execute until stall is resolved, then
  notify fetch
• Branch Stall/Mispredict
• Fetch insert X-bubbles
• Execute execute normally
• Trace Entry
• PC, Instuction Word, Instruction Executes

Fetch Process
ARM ISS
Execute Process
Microarch.Model
Exec Statistics
2-Process Model
Tool Flow
Base Model (Code) Strongarm (Additional Code) Xscale (Additional Code)
Changes to ISS (c) 1110 150 150
Metamodel files 832 191 197
Total 1942 341 347
Code Complexity Statistics
Metropolis Model SystemC Model
YAPI perf. 1500 60000
PIPE perf. 2240 -
Model Performance (Cycles/Sec on a 700 MHz Xeon)
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Bitfield Operands NumBits Encoding SingleEncoding
Anchors AnchorPoint
Connection Specifies the ordering of bitfields
Instruction Memory Ref Immediate
Constant Register Ref
Begin Anchor End Anchor Custom Anchor
Ordering Connection
ISA_ML Instruction Elements
State Elements WordSize Address Bits
Program Counter Source Register
ISA_ML State Elements
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Sample Instructions Other Instructions
Addition
Subtraction
Multiply Accumulate
Instruction 01 2...5 69 10..13 14..17 18..21 22..23 24..27 28..31
Arith Base 11 xxxx Rm Rn xxxx xxxx xx xxxx Rd
Addition 11 0111 Rm Rn xxxx xxxx xx config Rd
Subtractraction 11 0001 Rm Rn xxxx xxxx 00 config Rd
Multiply Accumulate 11 0011 Rm Rn Rmac xxxx xx xxxx Rd
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Constraints
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ICONS/Scratch