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Lecture 3 Power Consumption and Limiting Factors

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Title: Lecture 3 Power Consumption and Limiting Factors


1
Lecture 3Power Consumption and Limiting Factors
  • CMOS Deep-Submicron Power Dissipation
  • Limits to Low-Power Design near Si material
    limit
  • Plots of limiting factors
  • Summary
  • Michael L. Bushnell
  • CAIP Center and WINLAB, ECE Dept., Rutgers U.,
    Piscataway, NJ

2
CMOS Power Dissipation Short-Circuit Current
3
Short Circuit Current (contd)
4
Short Circuit Current (Concluded)
  • When input and output have equal rise and fall
    times, PSC is small.
  • If inverter is lightly loaded, so output tr, tf
    are shorter than input tr, tf then PSC becomes
    comparable to dynamic dissipation
  • Must make input tr, tf equal to output tr, tf

5
Dynamic Power Dissipation
CL VDD2 T
  • PD
  • Energy transferred/transition
  • Ave. Transitions/sec.

CL VDD2 2
2 T
6
Alternate Energy/Transition Method
7
Alternate Energy/Transition Method
8
Capacitance Calculation
  • Almost identical to methods in Digital VLSI
    Course
  • Interconnect C combined parallel plate and
    fringing C
  • W, H, L are width, height, length of metal wire

9
Limits to Low-Power Design
  • Moores Law Transistors/chip grows 1.5 X every
    year
  • Power-delay product (P td) declined by 1/105
    since late 1940s
  • Limits to low-power design
  • Fundamental
  • Material
  • Device
  • Circuit
  • System
  • Practical considerations

10
Five Key Principles
  • Using the lowest possible supply voltage
  • Using the smallest geometry, highest frequency
    devices but operating them at lowest possible f
  • Using parallelism and pipelining to lower
    required f
  • Power management by disconnecting power when
    system is idle
  • Designing systems with lowest requirements on
    subsystem performance for given user functionality

11
Fundamental Limits
  • Due to basic principles of thermodynamics,
    quantum mechanics, and electromagnetics,
    independent of devices, materials, circuits
  • Thermodynamics (P1) At any node with an R to
    ground, signal power Ps must exceed available
    noise power Pavail
  • g 1 is a constant, en2 is open-circuit
    mean-square V across R, k Boltzmanns constant,
    T absolute temperature, B node
    bandwidth
  • g 4 recommended, so Ps must be gt 0.104 eV (now
    larger by 107 factor)

12
Fundamental Limits (contd)
  • Quantum Mechanics (P2) Heisenberg Uncertainty
    Principle
  • In order to measure effect of switching
    transition of Dt interval, it must involve energy
    greater than h/Dt
  • P h / (Dt) 2
  • h Plancks constant
  • Electromagnetic Theory (iL2a(t)) Velocity of
    high-speed pulse on an interconnect of length L
    must always be less than c0 (speed of light in
    free space)
  • t is the interconnect transit time

13
Material Limits
  • Independent of devices and circuits
  • Consider semiconductor cube of undoped material
    of dimension Dx, embedded in 3D matrix of such
    cubes
  • Limit on switching energy and time (P3)
    calculated in terms of electrostatic energy
    stored in cube and transit time of a carrier
    through the cube
  • P ½ em Ec2 ss3 td2
  • ss carrier saturation velocity
  • Ec self-ionizing electric field strength
  • td cube transit time

14
Material Limits (contd)
  • Heat removal consideration (P4) Fouriers Law of
    heat conduction
  • P p K ss DT td
  • K thermal conductivity of semiconductor, A
    surface area of heat flow, DT temperature
    gradient
  • For Si, P/td 0.21 W/ns
  • For GaAs, P/td 0.69 W/ns (unsuitable)
  • Silicon-on-Insulator (SOI) Keq 0.029 KSi, 0.02
    KSi, 0.013 KSi (most suitable)

15
Material Limits (concluded)
  • Interconnect material limit (speed-of-light)
    (iL2b(t))
  • Propagation time through interconnect of length L
    of a material with relative dielectric constant
    er must be

16
Device Limits
  • Independent of circuits.
  • Minimum effective channel length Lmin gives limit
    on switching energy
  • E ½ C0 Lmin2 V02
  • Consider minimum transition times for Lmin 100
    nm (P4) and tox 3 nm (P7)
  • MOSFET already pushing against Si material limits
  • Limit on interconnect of length L RC response
    time
  • Drive by a unit step, so t 0 to 90 response
    time
  • t RC L2
  • r / Hr sheet resistance, e / He sheet
    capacitance
  • Limit on minimum interconnect response time

r e Hr He
17
Circuit Limits
  • Independent of system architecture.
  • Must distinguish between logic 0 and 1
  • VDD VDD,min
  • b between 2 and 4, T 300 K, VDD,min 0.1 V
  • This cannot be used because the threshold VT
    would be so small that drain leakage in off
    state would be unacceptable. Limit of VDD 1 V
    appears likely

b k T q

18
Circuit Limits (contd)
  • Switching energy per transition (P9)
  • E P td ½ Cro V02
  • Cro total CL of ring oscillator stage
  • Intrinsic gate delay time to charge/discharge
    load capacitance Cro
  • td
  • Leads to power
    constraint
  • Z channel width
  • CcV0
  • Ids

19
Circuit Limits (concluded)
  • Global interconnect limit (corner to corner)
    (iL2c (t))
  • Response time
  • t (2.3 Rtr Rint) Cint
  • Rtr Output resistance of driver, Rint lt 2.3 Rtr

20
System Limits
  • Chip architecture
  • Power-delay product of CMOS technology for the
    chip
  • Heat removal capacity of chip package
  • Clock frequency
  • Chip physical size
  • Selected architecture
  • Systolic array of 1024 identical square
    macrocells, each one of dimension L
  • 5-Level clock distribution H-tree
  • Maximum Manhattan distance for clock within
    macrocell is L, for logic signal it is 2L

21
System Limits (contd)
  • Limit on logic gate dimension
  • Arl1/2 Rrl M
  • Gate logic area is logic limited for nw 4 (
    wiring levels), pw 0.2 mm (wiring
    pitch), ew 0.75 (wiring efficiency factor)

  • Rrl 6, M 3, and for other values
  • td tdrl
  • Heat removal limit average power dissipation of
    composite gate P must be less than cooling
    capacity of packaging
  • P QA
  • Q package cooling coefficient
  • A substrate area occupied by critical path
    composite gate

pw ew nw
Tcc ncp

22
System Limits (concluded)
scp ncp a
Ccc ncp Crl
  • P (1/2 Crl V02)-2 (1 ) td2 (
    Q Arl)3
  • Locus P11 (t)
  • Crl MOSFET diffusion C wiring C gate C
  • Ccc corner-to-corner interconnect C
  • ncp random logic gates on critical path
  • scp gt 1 (clock skew factor)
  • Arl random logic area
  • Q package cooling coefficient
  • a probability that gate switches during a clock
    interval

23
Practical Limits
  • Beyond a certain limit of scaling, cost of
    designing, manufacturing, testing, and packaging
    will cause the cost/function to level off and
    start increasing
  • transistors/chip N F-2 D2 PE
  • F feature size (0.0625 mm in 2020), D chip
    area in 2020 (gt 50 mm2), PE packaging
    efficiency in 2020
    (1 transistor/minimum feature area)
  • Leads to possibility of 100 billion transistor
    chips

24
P Limits Plotted
P7 Device Transition Time P8 Missing P9
Transistor Switching Energy P10 Missing P11 Heat
Removal P12 Missing
P1 Thermodynamics P2 Heisenberg Uncertainty
Principle P3 Electrostatics P4 Heat Conduction P5
Missing P6 Missing
25
Interconnect Limits Plotted
Speed of light Speed of light Wire length Missing
26
Summary
  • CMOS Deep-Submicron Power Dissipation all 3
    factors (dynamic, short circuit, and leakage) are
    now important
  • There are limits to Low-Power Design we are
    near Si CMOS material limit
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