Csci 136 Computer Architecture II

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Csci 136 Computer Architecture II Summary of
MIPS ISA

• Xiuzhen Cheng
• cheng_at_gwu.edu

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Announcement

• Homework assignments 2
• Readings Sections 3.6, 3.7, 3.10, 3.11, 3.13,
  3.14
• Problems 3.5, 3.10, 3.12, 3.22, 3.23, 3.24, 3.25
• Project 1 is due on 1159PM, Feb 13, 2003.

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What is an ISA?

• A very important abstraction
• Provide the interface between the low-level
  software and hardware
• May have multiple hardware implementations
• Needs to answer the following questions
• What is the minimum instruction set to be
  supported?
• Use general purpose register or not?
• CIRS or RISC design?
• Instruction format?
• Addressing mode?

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Basic ISA Classes

• Accumulator Architecture
• Stack Architecture
• Load-Store (General Purpose Register)
  Architecture
• Register Register
• Register Memory
• Memory Memory
• Code sequences for (CAB) for 4 classes of
  instruction set

Stack
Accumulator
Push A
Load A
Load R1,A
Push B
Add B
Load R2,B
Add
Store C
Add R3,R1,R2
Pop C
Store C,R3
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General Purpose Register Dominates
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Memory Addressing

Since 1980 almost every machine uses addresses to
level of 8-bits
(byte)

2 questions for design of ISA

Since one could read a 32-bit word as four loads
of bytes from
sequential byte addresses or as one load word
from a single byte
address, How do byte addresses map onto words?
Can a word be placed on any byte boundary?

What about MIPS?
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ISA Operation Summary
Support these simple instructions, since they
will dominate the number of instructions
executed load, store, add, subtract, move
register-register, and, shift, compare equal,
compare not equal, branch, jump, call, return
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Summary Salient features of MIPS

• 32-bit fixed format inst (3 formats)
• 32 32-bit GPR (R0 contains zero) and 32 FP
  registers (and HI LO)
• partitioned by software convention
• 3-address, reg-reg arithmetic instr.
• Single addressing mode for load/store
  basedisplacement
• no indirection, scaled
• 16-bit immediate plus LUI
• Simple branch conditions
• compare against zero or two registers for ,?
• no integer condition codes

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Summary MIPS Instruction set design

• Use general purpose registers with a load-store
  architecture yes or no?
• Provide 32 general purpose registers plus
  separate floating-point registers
• Whats the addressing mode supported by MIPS?
• Use fixed instruction encoding if interested in
  performance and use variable instruction encoding
  if interested in code size

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Summary MIPS Instruction set design

• Support these data sizes and types 8-bit,
  16-bit, 32-bit integers and 32-bit and 64-bit
  IEEE 754 floating point numbers
• Support these simple instructions, since they
  will dominate the number of instructions
  executed load, store, add, subtract, move
  register-register, and, shift, compare equal,
  compare not equal, branch, jump, call, and
  return
• Aim for a minimalist instruction set

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MIPS Hardware Design Principles

• Simplicity favors regularity
• Keeping the hardware simple!
• R-Type instruction format
• Smaller is faster
• 32 general purpose registers, no more, no less.
• Good design demands good compromises
• R, I, J, 3 types of instruction formats
• Make the common case fast!
• I-type instructions for constant numbers

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In-Class Exercise Reverse a String

• Write a MIPS procedure to reverse a
  null-terminated character string. Assume the
  address of the string is in a0 and the address
  of the reversed string is in a1. Also assume the
  spaces needed by the reversed string have been
  pre-allocated.

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In-Class Exercise Reverse a String

• Write a MIPS procedure to reverse a
  null-terminated character string. Assume the
  address of the string is in a0 and the address
  of the reversed string is in a1. Also assume the
  spaces needed by the reversed string have been
  pre-allocated.

reverseStr addiu sp, sp, -32 sw s0,
16(sp) sw s1, 20(sp) move s0,
a0 move s1, a1 addi sp, sp, -1 sb zero,
0(sp) push lbu t0, 0(s0) beq t0, zero,
pop addi s0, s0, 1 addi sp, sp, -1 sb t0,
0(sp) j push
pop lbu t0, 0(sp) addi sp, sp, 1 sb t0,
0(s1) beq t0, zero, done addi s1, s1,
1 j pop done lw s0, 16(sp) lw s1,
20(sp) addi sp, sp, 32 jr ra
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Questions?