DESIGN AND IMPLEMENTAION OF A DDR SDRAM CONTROLLER FOR SYSTEM ON CHIP - PowerPoint PPT Presentation

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DESIGN AND IMPLEMENTAION OF A DDR SDRAM CONTROLLER FOR SYSTEM ON CHIP

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2002-12-13. DESIGN AND IMPLEMENTAION OF A. DDR SDRAM ... EMRS (Extended MRS) MO/EAB/RTN/D Magnus Sj lander. 2002-12-13. 8. DDR SDRAM Memory Controller ... – PowerPoint PPT presentation

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Title: DESIGN AND IMPLEMENTAION OF A DDR SDRAM CONTROLLER FOR SYSTEM ON CHIP


1
DESIGN AND IMPLEMENTAION OF A DDR SDRAM
CONTROLLERFOR SYSTEM ON CHIP
  • Magnus Själander

2
Contents
  • Double Data Rate Interfaces
  • DDR SDRAM Architecture and Functionality
  • DDR Memory Controller
  • Data Resynchronization
  • Floorplan and Place Route
  • Future Work
  • Conclusion

3
Double Data Rate Interfaces
  • New
  • Data Transmissions on rising and falling edge
  • Data Strobe
  • Advantages
  • Time of Flight
  • Clock Skew
  • Pin Count
  • Bandwidth
  • Disadvantage
  • Synchronization

4
SDRAM Architecture
  • Four Banks
  • Row and Column Select Lines
  • 1T Memory Cells
  • Sense Amplifiers
  • Global Data Path

5
DDR SDRAM Architecture
  • 2n-prefetch
  • Delay Lock Loop

6
DDR SDRAM Improvements
  • Long Delay in Column Decode and Data Lines
  • Added a Delay Lock Loop to Increase Clock
    Frequency

7
DDR SDRAM Commands
  • Same Commands as for Standard SDRAM
  • READ
  • WRITE
  • ACTIVATE
  • PRECHARGE
  • REFRESH
  • MRS (Mode Register Set)
  • Added
  • EMRS (Extended MRS)

8
DDR SDRAM Memory Controller
9
Core Memory Controller
10
AHB Interface
11
Arbiter
12
Capturing the Data
  • Phase Shift the Data Strobe
  • Resynchronize the Data

13
Phase Shift the Data Strobe
  • Delay Lock Loop
  • Inverter Delay
  • PCB Line Delay
  • Programmable Delay Line with Temperature Sensing

14
Synchronization of the Data
  • One Flip-Flop for each Flank to Sample

15
Synchronization of the Data Continued
16
Synchronization of the Data Continued
  • Simplified Phase Detector

17
Floorplan
18
Place Route
19
Future Work
  • Improved Refresh Handling
  • Attempt to Reduce Initial Latency for Bursts
  • Improved Buffer Handling

20
Conclusion
  • Working Implementation
  • Smaller Changes to Improve Performance
  • Highlights Difficulties and Solutions

21
Questions ?
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