Instruction Set Architecture

1
Instruction Set Architecture

• Chapter 5

2
Overview

• Sits between the compiler and hardware

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Properties

• A good ISA
• Ease of implementing on current hardware
• Provide clean target for compile code
• Defines how the machine appears to machine
  language programmer
• Some architectures provide a formal definition
• Allows reproduction of compatible hardware
  spark
• Other do not want reproduction Pentium
• Two modes of operation kernel and user

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Memory Models

• Memory divided into cells with consecutive
  addresses common 8-bits, 16-bits, words.
• Instruction available to manipulate words.
• Many architectures expect words to be aligned on
  natural boundaries for efficient operation.

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Addressing

• Many machines have a single linear address space
  for instructions and data. I.E. 232.
• Some machines have different addresses for data
  and instructions.
• More complex. Has two advantages.
• Shorter address space.
• Usual pattern LOAD followed by STORE.
• Instruction reordering destroys this pattern.
• Some have SYNC instructions.

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Registers

• A subset of registers available at the
  micro-architecture levels are available at the
  ISA level.
• TOS, MAR not visible.
• PC, stack pointer available.
• Two categories of registers.
• Special purpose PC, stack pointer.
• General purpose for saving program variables and
  intermediate values of computations.
• General purpose registers
• Completely symmetric I.E. R1 can replace R24.
• Somewhat specialized EDX for half pdt/div in
  Pentium.
• Assembly language programmers use system wide
  conventions in using general purpose registers.

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Program Status Word

• A flag register.
• N negative.
• Z zero.
• V overflow.
• C carry from leftmost bit .
• P even parity.
• Readable I user mode, but some fields written
  only in kernel mode.

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Instructions Pentium

• Control what hardware can do.
• Has LOAD and STORE instructions.
• Pentium has 3 modes for backward compatibility.
• Real mode all features since 8088 turned off.
• Runs like a 8088, crashes if something goes
  wrong.
• Virtual 8086 mode runs 8088 in a protected mode.
• Like before, runs in special environment, does
  not crash if something goes wrong.
• Protected mode runs like a pentium.
• 4 levels 0- kernel, 3-user, 1, 2, rarely used.
• Address space 232 bytes 32 bit words, little
  endian.

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Pentium Instructions

• Group 1 general purpose 32-bit registers.
• EAX arithmetic, EBX pointers, ECX looping EDX
  multiplication/division.
• Group 2 general purpose 32-bit registers.
• ESI source string, EDI destination string.
• EBP base of local stack, ESP local stack
  pointer.
• Group 3 segment registers.
• EIP program counter.
• EFLAGS PSW.

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Pentium Registers
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Other Concepts Register Window

• Have multiple sets of registers only one set is
  visible at any time (called register window).
• CWP current window pointer says which set.
• Can implement procedure calls efficiently.
• Decrementing CWP switches from caller to calee.
• Some registers are common efficient parameter
  passing mechanism.
• Does not work well with deeply nested calls.
• Need to kick out old stacks and get new calees.

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Example Register Window
Available in Spark
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Other Features Heap

• Heap to allocate dynamic memory.
• Example int a new int4096.
• Use a special area called the heap.
• When heap runs out, need to throw out words, just
  like in cache updates.
• Garbage collector software does this.
• Used in IJVM. Read section 5.1.7.

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Data Types

• Numeric
• Integer signed or unsigned- stored in twos
  complement etc.
• Floating point. Stored in IEEE standards etc.
• Non numeric
• Character ASCII, UNICODE formats.
• Character strings.
• Boolean value.Bit maps words where each bit
  records TRUE or FALSE.

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Example Data Formats
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Instruction Formats

• Instruction Opcode addressing.

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Instruction Formats

• Smaller instruction take less space and less
  bandwidth from memory to processor.
• Decoding takes times. Simpler the better.
• Sufficient room for IS to express all operations.
• N bits encode only 2N instructions.
• Number of bits in address field.
• Finer memory access requires longer addresses.

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Opcode Vs. Address Space

• Nk bit instructions
• 2k opcode, n bit addresses.
• 2(k1) opcode, n-1 bit addresses.
• Either small number of cells addressed or poorer
  address resolution.
• Expanding opcode say need .
• 4-bit opcode and 15, 3-addresses instructions,
  14, 2-address instructions, 31, 1-address
  instructions, and 16 no address instructions.
• Need to encode instructions in a specific way.

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Expanding Opcode Example

• 14, 2-address opcodes have 1111 in leftmost bits,
  etc.

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Addressing

• Format Instruction, add1, add2, add3
• Every address takes space.
• Ways to save space
• Load into registers before using I.e. LOAD
  operands and use ADD on registers
• Saves repetitive LOADing
• Shorter addresses
• Use implicit addressing
• If addition meant Register2 Register2Source1

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Addressing Modes

• Immediate Addressing
• Example MOVE R1, 4
• Operand _at_ address 4 fetched same time instruction
  is fetched.
• No or little decoding necessary
• Direct Addressing
• Address is given directly as above.
• Disadvantages cannot move data around. Address
  need to be known at compile time.

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Addressing Modes

• Register addressing
• Used mostly.
• Register indirect (pointer) addressing
• Address passed in the register. The instruction
  does not need to know the address.

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Indexed Addressing

• Addressing consecutive memory with known offsets
  arrays
• Example of AND-ing two arrays A1024 and
  B1024, and OR-ing the result.
• R1 holds accumulated OR value.
• R2 holds the index I.
• R3 holds 4096- lowest value not used.
• R4 scratch register holding each product

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Base-Indexed Addressing

• Address computed by adding two registers an
  (optional) offset.
• Example
• LOOP MOV R4, (R2R5)
• AND R4, (R2R6)

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Comparison of Addressing Modes
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Reverse Polish Notation

• Operator after the operands
• Example A,B ADD
• Advantages
• Formulas can be written without parenthesis
• Easy computation on a stack.
• Avoids arbitrary infix precedence rules.
• There are several algorithms to convert from one
  form to another

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Example Reverse Polish
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Evaluating Reverse Polish on Stacks
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Other Issues in Addressing

• Addressing for Branch Instructions
• Can use direct, indirect or indexed modes
• A good design is given below

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Instruction Types

• Data Movement
• Source (Register, memory)-gtDestination (Register,
  memory)
• LOAD Memory -gt Register
• STORE Register -gt Memory
• MOVE Register -gt Register
• Nothing to move from memory to memory
• Usually moves words, or some ISAs can be told by
  how much (half word to many words at a time)

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Operations

• Dyadic Operations
• Have to inputs and (mostly) one output.
• Include arithmetic and logical operations.
• Monadic Operations
• One input, (mostly) one output
• Shorter because of single operand
• Shift, rotate, NOT, Inverse
• Special Dyadic Operations as monadic
• Adding one INC

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Operations

• Comparisons and Conditional Branches
• If ZERO go to LABEL
• Used for loops, overflows etc.
• Procedure Calls
• Proceduresubroutinemethod a separate piece of
  code doing a logic unit of work
• Must pass address to invoke
• Must return back after caller finishes can be
  placed in memory, register or stack
• Can implement recursion this was I.e. a
  procedure calling itself

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Loop Control

• Loop is implemented by having some counter and a
  conditional.
• Checking can be done at the beginning, middle or
  end.
• Most high level languages allow arbitrary nesting
  of loops.

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Input/Output

• Programmed I/O
• Every character is transferred by explicitly
  calling a READ/WRITE instructions.
• Can used memory mapped I/O
• I.e. special purpose registers have memory
  addresses. Writing to or reading these addresses
  updates values in corresponding register
• Otherwise IN OUT instructions are needed

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Input/Output

• Disadvantages
• Wasting CPU cycles fro I/O
• How it works
• CPU waits in a loop (busy waiting) reading status
  register. When data available, it reads

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Interrupt Driven I/O and DMA

• CPU starts I/O device. Let it generate an
  interrupt when the job is done.
• Disadvantages Too many interrupts generated.
• DMA usually has separate chip do the I.O transfer
  for the CPU. When the job is done one interrupt
  is generated.

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Flow of Control

• Execution of instruction sequences
• Executes one after the other, if not explicitly
  stated to do so.
• What makes it do otherwise?
• Procedure calls
• Co-routines
• Traps and interrupts

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Behavior of PC
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Procedures

• Transfers control to a new place, and executes
  sequentially. When finished, transfers control
  back to where it left off.
• Interesting addition Recursive Procedures

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Procedure Calls Stack Implementation

• Procedure Prolog Advance stack pointer and
  reserves space for local variables
• Procedure Epilog Cleaning up before call return

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Co-routines

• Caller-calee relationship in procedure calls

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Caller-Calee in Co-Routines
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Traps

• Automatic response to an unusual condition
• Examples
• Underflow/overflow, stack overflow, protection
  violation, undefined opcode, division by 0,
  non-existent device, addressing error
• Calls trap handler, stored at fixed location
• Can be implemented in HW or micro-program

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Interrupts

• Changes to a running program caused by some
  external condition such as I/O ready
• Causes to stop running program, and transfer
  control to interrupt handler.
• Traps synchronous (caused by running code),
  interrupts (caused by some one else)
  asynchronous.
• Consider example interrupt from textbook where
  the machine is trying to write a line on treminal

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Hardware Actions

• Device controller asserts an interrupt on busline
• CPU acknowledges when its ready
• Puts interrupt vector (number)
• CPU pushes PC and PSW onto stack
• CPU locates new PC for interrupt service routine
  by looking at interrupt vector.

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Software Actions

• Interrupt service routine saves all registers
• Find terminal number by reading device register
  to get which device interrupted. Read status etc
• If I/O interrupted handle interrupt.
• In needed execute special code to let device know
  that interrupt was handled.
• Restore registers
• Execute RETURN FROM INTERRUPT to put CPU back in
  charge.

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More on Interrupts

• Interrupts are handled transparently.
• Interrupting an interrupt
• Disable all other interrupts.(masking)
• Have prioritized interrupts.
• Now transparency is very important.
• Maskable and Non-maskable interrupts
• Non maskable used for near catastrophic faults
  such as parity errors.
• Some machines have external interrupt controllers
  to hold back low priority interrupts

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Multiple Interrupts Example