Clockless%20Logic%20and%20Silicon%20Compilers

1
Clockless Logic andSilicon Compilers

• Montek Singh
• Tue, Jan 17, 2006

2
Preliminaries

• How is data represented in an asynchronous
  system?
• How is information exchanged? control
  signaling (handshake styles)

3
Data Encoding Bundled Data

• Single-rail Bundled Datapath simplest approach
  
• widely used
• Features
• datapath 1 wire per bit (e.g. standard sync
  blocks)
• matched delay produces delayed done signal
• worst-case delay longer than slowest path

• Practical style can reuse sync components small
  area
• Fixed (worst-case) completion time

4
Bundled Data Completion Sensing

• Delay Matching
• either single worst-case delay
• or, fine-grain delay

• Speculative completion
• choose delay on the fly
• start with shortest delay increase as needed

5
Data Encoding Dual-Rail

• Dual-rail uses 2 wires per data bit

Each Dual-Rail Pair provides both data value and
validity

• provides robust data-dependent completion
• needs completion detectors

6
Dual-Rail Completion Sensing

• Dual-Rail Completion Detector
• combines dual-rail signals
• indicates when all bits are valid (or reset)

• C-element
• if all inputs1, output ? 1
• if all inputs0, output ? 0
• else, maintain output value

• OR together 2 rails per bit
• Merge results using a Müller C-element

7
Handshaking Styles 4-phase

• 4-Phase requires 4 events per handshake

• Level-sensitive ? simpler logic implementation
• Overhead of return-to-zero (RTZ or resetting)
• extra events which do no useful computation

8
Handshaking Styles 2-phase

• 2-Phase requires 2 events per handshake
• a.k.a. transition signaling

• Elegant no return-to-zero
• Slower logic implementation
• logic primitives are inherently level-sensitive,
  not event-based (at least in CMOS)

9
Handshaking Styles Pulse Mode

• Pulse Mode combines benefits of 2-phase and
  4-phase
• use pulses to represent events

start next event
start event
Request
next event done
event done
Acknowledge

• No return-to-zero (like 2-phase)
• Level-based implementation (like 4-phase)
• Need a timing constraint on pulse with

10
Handshaking Styles Single-Track

• Single-Track combines req and ack onto single
  wire!
• one wire used for bidirectional communication
• sender raises, receiver lowers

• Efficient protocol no return-to-zero,
  level-based
• Need aggressive low-level design techniques
• much effort to ensure reliability

11
Handshaking Data Representation

• Several combinations possible
• dual-rail 4-phase, single-rail 4-phase, dual-rail
  2-phase, and single-rail 2-phase
• Example dual-rail 4-phase

A
B

• dual-rail data functions as an implicit
  request
• 4-phase cycle between acknowledge and implicit
  request

12
Other Data Representation Styles

• Level-Encoded Dual-Rail (LEDR)
• 2 wires per bit data and phase
• exactly one wire per bit changes value
• if new value is different, data wire changes
  value
• else phase wire change value
• M-of-N Codes
• N wires used for a data word
• M wires (M lt N) change value
• Values of N and M have impact on
• information transmitted, power consumed and logic
  complexity
• Knuth codes, Huffman codes,

13
Which to use?

• Depends on several performance parameters
• speed
• single-rail vs. dual-rail
• single-rail may be faster (if designed
  aggressively)
• dual-rail may be faster (if completion times vary
  widely)
• 2-phase vs. 4-phase
• 2-phase may be faster (if logic overhead is
  small)
• 4-phase may be faster (if overhead of
  return-to-zero is small)
• power consumption
• 2-phase typically has fewer gate transitions (?
  lower power)
• amount of logic used (gates/wires/pins ? chip
  area)
• single-rail needs fewer gates/wires/pins
• design and verification effort
• dual-rail, 1-of-N, M-of-N, Knuth codes
• delay-insensitive robust in the presence of
  arbitrary delays
• single-rail requires greater timing
  verification effort