The ESD Challenge At

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The ESD Challenge At 90nm CMOS Technologies and
Beyond Robert A. Ashton rashton_at_whitemountainlabs
.com
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Outline

• Introduction to ESD ESD Protection
• Technology Advances and ESD
• Intrinsic Changes in Technology
• Challenges new Technology Introduces
• Discussion of Specific Issues
• Directions for ESD Protection Control
• Summary

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The ESD Threat It Does Not Change

• ESD threats we test for
• Charged Human Touches IC (HBM)
• Charged Machine Touches IC (MM)
• Charged IC Discharges (CDM)
• Elements That Define Tests
• A Capacitance That is Charged
• A Discharge Path

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Elements That Define ESD Testing
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HBM 2000V, MM 200V, and CDM 500V
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ESD Protection Thought Process

• Think
• High Current Flow/Short Time Scale
• NOT High Voltage
• Most of Voltage Drop Outside of Device
• High Current generates Voltage On Chip
• On Chip Voltages Often lt10V
• ESD Design
• Create Low Resistance Paths
• Keep Voltage and Current Below Critical Levels

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Sample ESD Protection Strategy
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Stress IN Negative To VSS1
Voltage Drop One Forward Bias Diode Bus
Resistance
Diode Drop NOT Low Current, 0.7V, but at HIGH
current, at least a Full Volt
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Stress IN Positive To VSS1
Voltage Drop 1 FB Diode Rail Clamp Bus
Resistance
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ESD Strategy Multi Power Supply
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Stress OUT Positive To VDD1
Voltage Drop 3 FB Diode Rail Clamp Bus
Resistance
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ESD and Technology Evolution

• New Technologies Change
• Critical Voltage Levels
• Critical Current Levels
• Change Resistances

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Intrinsic Technology Changes

• Feature sizes get smaller (DUH!!!)
• Thicknesses get thinner
• Not just gate oxide
• Metal layers
• Junction depths
• Sheet resistances increase
• New materials
• Metals, Low and High K dielectrics,
• New silicide materials (changes junctions)
• High resistance starting material
• Modified implants for transistor junctions

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Changes Technologies Facilitate

• Higher Pin Counts
• Analog and Digital On One Chip
• Multiple Power Domains
• Higher Frequencies
• Passive Components on Chip

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Intrinsic ESD Technology Issues

• Will Discuss
• Transistor behavior
• Gate Dielectric
• Interconnect
• Will Not Discuss
• Silicide Changes
• Diffusion Resistance
• Other Material Changes

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nMOS Transistor Behavior

• nMOS Split Personality
• Can be weak link in ESD strategy
• Can be a robust ESD protection device
• What are ESD properties of transistor?
• How do they scale with technology?

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Grounded Gate nMOS
Drain
Gate
Source
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GG nMOS Parameters and ESD

• Vt1, It1 How easy to turn on snapback
• Vt1, generally lowers with technology
• Important relative to other voltages
• Vsb Energy during ESD event
• Needs to be above VDD max and burn-in V
• Vt2, It2 Defines damage point
• It2, general transistor robustness
• Either way with technology
• Vt2, important relative to other voltages

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nMOS Generation to Generation

• TI Transistor study
• Requirement same for each generation
• ESD performance similar over several generations
• (Boselli et.al. 2005 EOS/ESD Symposium)
• Dont take this as a given!!!
• Changes could have dramatic consequences

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Oxide Versus Junction Breakdown
Weir , IRPS 2004 (based on Duvvury Semi. Sci.
Tech. 1996)
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How Do Oxides Survive?

• Oxide BD dropping faster than Junction BD
• What allows Passing ESD Tests
• Time Dependent Dielectric Breakdown
• TDDB
• Higher survival Voltage at shorter times
• Extends to the ESD time scale

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Time Dependent Dielectric Breakdown
For a specific Oxide and Area
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Equivalent Oxide Thickness
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Oxinitride to High K Transition

• Oxinitride
• 1.2nm oxinitride can survive 3.4V at ESD times
• Thinner dielectric, safe voltage decreases
• Will high K materials depend similarly?
• Will need to be determined

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Intermediate Interconnect Trend
Int. Tech. Roadmap for Semiconductors 2004
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Chip Size Trend
Int. Tech. Roadmap for Semiconductors 2004
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Interconnect and ESD

• Allowed ESD IR drop same or decreasing
• Sheet resistance increasing
• Chip size not decreasing
• Push to reduce line widths
• Increased care needed in ESD current paths

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Extrinsic ESD Technology Issues

• New Technologies Make Possible
• High Frequency (RF) Circuits
• Increased Number of Pins
• Increasing Number of Power Domains
• Analog and Digital on Same Chip
• Passive Components on Chip
• ESD Implications are intertwined
• Long Test Time
• Multiple Zaps ?Wear Out?
• Multiple ESD Strategies On One Chip

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High Frequency in Advanced Technology

• Increased integration of RF
• RF requires low capacitance
• ESD protection eats capacitive budget
• Compromises are made w.r.t. ESD
• Lower ESD Level for RF pins
• Locate RF pins at less susceptible locations

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HBM/MM Pin Combinations in Test
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Zap dependence on Pins and Power Domains
Number of Power Domains
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HBM Test Time (assume 1s per zap)
Number of Power Domains
Time to Test is an Issue
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Multiple Zap Wear Out
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The Bottom Line on The Future

• ESD Association Roadmap to 2010
• We can not expect ESD levels to stay the same!

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ESD Roadmap - HBM
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ESD Roadmap - CDM
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How Industry Will Cope On Chip

• More Active Circuits for ESD Protection
• Triggered by Power Supply Transient
• Normal MOS (or bipolar) current for protection
• Protection can be circuit (SPICE) simulated
• Less prone to wear-out
• Increased use of ESD design simulation
• Biggest development needed in CDM
• Package Power Planes reduce IR drop
• Narrow Band RF circuits
• Use Inductor Matching Network as part of
  Protection

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How Industry Will Cope Off Chip

• Improved ESD control in factory
• Improved training
• Better handling equipment
• Air Ionization
• Monitoring of ESD events
• Increased Off Chip ESD protection
• Use on select pins (RF for example)
• Zener Diodes
• Polymeric voltage suppression

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Summary ESD at 90nm and Below

• The Challenge Increases
• Everyone needs to share the pain
• Technologists Squeeze in Robustness
• Designers
• ESD design from day one
• Development of improved ESD prediction tools
• Testing Break testing into sub units
• Modified Pin Combinations (not full coverage?)
• System Designers Provide protection on board
• Factory Improved ESD Control