Impact of Leakage and Variations on Sense Amplifiers for OnChip SRAMs

1
Impact of Leakage and Variations on Sense
Amplifiers for On-Chip SRAMs

• M.S. Thesis Proposal by
• Aiyappan Natarajan
• Chair Prof. Wayne Burleson
• Interconnect Circuit Design Group
• University Of Massachusetts Amherst
• This project was funded by Intel Corp.

2
Outline

• Introduction
• Motivation Issues in Sub-100nm CMOS
• Sense Amplifier Circuits
• Bitline Leakage Compensation
• Experimental Setup and Methodology
• Results
• Proposed Work - Timeline
• Conclusions

3
Introduction

• Sub-100nm issues
• Leakage current and intra-die variations increase
• On-chip memory size getting bigger
• Increase in bitline capacitance
• Memory performance is important (Sense
  Amplifiers)
• Problem Statement
• This thesis evaluates 4 differential sense
  amplifiers in terms of delay and energy using a
  70nm CMOS technology under the interaction of
  increasing
• Bitline capacitance
• Bitline leakage
• Intra-die variations

4
Motivation

• Issues in sub-100nm CMOS technologies
• Increasing variations in intra-die device and
  environment
• Reduced Device Dimensions
• Fabrication Process
• Operating conditions
• Increasing leakage current
• Supply voltage (VDD) and threshold Voltage (Vt)
  reduction due to scaling

5
Variations

• Device Variation
• Geometry Variations
• Effective channel length (Leff - 40 variation )
• Electrical Parameter Variation
• Threshold voltage (Vt - 10 variation)
• Environmental Variation
• Temperature (30)
• Power Supply (10)

(180nm)
(100nm)
(70nm)
(130nm)
Year
Device and interconnect (intra-die) variation
trends for different technology generations
D.Boning, Models of process variations in
device and interconnect, in Design of
High-Performance Microprocessor Circuits, A.
Chandrakasan, W. Bowhill and F. Fox, IEEE Press
2001
6
Leakage Current with Technology
V.De, Intel 2001
7 times

• Subthreshold leakage current is dominant
• Exponentially dependent on temperature and Vt
• Increasing leakage current with die area

Above simulations matched with the projected off
currents given by Intel in Design of
High-Performance Microprocessor Circuits, A.
Chandrakasan et al., IEEE Press 2001
7
Memory System Design

• Microprocessors need for faster and larger
  memories is increasing with technology
• On-chip memories constitute an increasing portion
  of transistor count
• (60 for Alpha 21264 Gieseke et al. )
• Performance, power and yield of microprocessor is
  highly dependent on memory design
• This need for bigger and faster on-chip memories
  increases
• Bit-line Capacitance
• Leakage Currents
• Impact of Variations

8
Memory System

• Critical path of memory system for read operation
• Address Register
• Row Decoder
• SRAM column
• Sense Amplifier
• Comparator
• Output Buffer

SRAM Array
ROW DECODER
ADDRESS REGISTER
Address
Column Mux
COLUMN DECODER
COLUMN DECODER
Sense Amplifiers
Input/Output Register
Comparator
Information Bits
CMOS Memory Circuits by Tegze P. Haraszti,
Kluwer 2001
9
Effect of Bitline Capacitance

• Dependent on number of cells per column
• S (Ci)acc
• Interconnect Capacitance
• Small cell size weak driver
• Bitline switching is slow
• Solution
• Differential sense amplifiers
• Precharge

n
i 0
10
Leakage in Memories

• Cell Leakage
• Currents through MN3 and MP2
• Static Power Dissipation when cell not accessed
• Bitline Leakage
• Currents through access devices (MN5 and MN6)
• Drops signal amplitude in bitlines
• Affects the memory performance

V(Q) Vdd V(Q) 0 V
11
Bitline Leakage
WL_0

• Number of Cells per column
• Data stored in the cells
• Worst case leakage
• All cells but one store same data
• Topmost one accessed
• Modeled as a noise
• Delays bitline differential development
• Solution
• Compensate the bitline leakage
• Bitline leakage compensation Agawa et al.
• Reduce the number of cells per column

1
0
Icell0
Icell1
Ileak1
Ileak2
12
Sense Amplifier Circuits

• Amplify small signal difference in bitlines to
  CMOS voltage levels
• Improve memory performance
• Energy efficient as highly capacitive bitlines
  dont swing full-rail
• Voltage-mode
• Cross-Coupled Inverter Latch (C2IL)
• Alpha Latch
• Current-mode
• Clamped Bitline Sense Amplifier (CBLSA)
• Modified Differential Current Sense Amplifier
  (MDCSA)
• Izumikawa Current Sense Amplifer (ICSA)
• Charge-Transfer Sense Amplifier (CTSA)

13
Voltage-mode Sense AmplifierCross-Coupled
Inverter Latch (C2IL)

• Bitlines coupled to output node
• Bitlines terminated at the gates of the two
  inverters
• Cross-coupled inverter pair provides high-gain
• Voltage difference in the input nodes amplified
  to CMOS levels by the latch

T. Uetake et al., A 1.0ns access 770Mhz 36kb
SRAM macro, In ISSC Dig. Tech. Papers ,
pp.176-177, Feb 1997
14
Functionality of C2IL Read Cycle
t1
t2
Total Delay t1 t2
15
Voltage-mode Sense AmplifierAlpha Latch

• Two additional NMOS devices
• Isolates input and output nodes
• High input-impedance
• High probability of device mismatch

B. Gieseke et al., A 600 Mhz superscalar RISC
Microprocessor with out of order execution, IEEE
JSSC, 542-548, 1991
16
Functionality of Alpha LatchRead Phase
17
Current mode Sense Amplifiers

• Performance of voltage-mode depends on
  differential discharging of the bitlines
• Increase in bitline capacitance increases the
  sensing delay
• Current-mode sense amplifiers provide low-input
  impedance
• Reduced effect of bitline capacitance
• Amplify the current difference in the bitlines
  and hence are faster than voltage-mode

18
Current-mode Sense AmplifierClamped Bitline
Sense Amplifier (CBLSA)

• Low-input impedance provided by MN3 and MN3B
• Amplifies current difference (MN3 and MN3B)
• Cross-coupled inverters
• Bitlines are pulled-down

T. N. Blalock, and R. C. Jaeger, "A High- Speed
Clamped Bit-Line Current-Mode Sense Amplifier,"
IEEE JSSC, pp. 542-548, Apr. 1991.
19
Functionality of CBLSARead Phase
20
Modified Differential Current Sense Amplifier
(MDCSA)

• Simple Four Transistor (SFT)
• Provides virtual short-circuit to bitlines
• Maintains almost the same potential
• Modified CBLSA circuit as second stage
• Input and output nodes are isolated
• Low-swing in the bitlines

M.Sinha, Low-Voltage Sensing Techniques for
High-Speed On-Chip Global Interconnects and
Caches, MS Thesis, ICDG, UMass Amherst
21
Functionality of MDCSARead Phase
22
Bitline Leakage Compensation (BLC)

• Bitlines precharged to Vdd-Vtp
• Detects and measures the bitline leakage current
• Stored in a capacitor (CAP7)
• Injects the same leakage current into the
  bitlines during read phase

K. Agawa et. al , A Bitline Leakage Compensation
Scheme for Low-Voltage SRAMs, IEEE JSSC, Vol.
36, No. 5, May 2001
23
BLC Timing Precharge phase TA
K. Agawa et. al , A Bitline Leakage Compensation
Scheme for Low-Voltage SRAMs, IEEE JSSC, Vol.
36, No. 5, May 2001
24
BLC Timing Precharge phase TB
K. Agawa et. al , A Bitline Leakage Compensation
Scheme for Low-Voltage SRAMs, IEEE JSSC, Vol.
36, No. 5, May 2001
25
BLC Timing Precharge phase TC
K. Agawa et. al , A Bitline Leakage Compensation
Scheme for Low-Voltage SRAMs, IEEE JSSC, Vol.
36, No. 5, May 2001
26
BLC Timing Read cycle TD
K. Agawa et. al , A Bitline Leakage Compensation
Scheme for Low-Voltage SRAMs, IEEE JSSC, Vol.
36, No. 5, May 2001
27
Read Phase of C2IL with BLC circuit(Worst Case
Leakage)
200ps
120ps
No BLC Circuit
With BLC circuit

• Both the bitlines are pulled down for worst case
  leakage condition
• With BLC circuit BL stays high while BL is
  pulled down
• Bitline differential develops more quickly

28
Experimental Set-up

• Memory column with varying number of cells
  32,64,128, 256 and 512
• Topmost cell stores a 1 and rest of the cells
  store a 0
• Topmost cell accessed
• Worst case delay and leakage
• One Sense Amplifier shared by four memory columns
• Bitlines precharged to Vdd

29
Assumptions

• All circuits were designed in a 70nm CMOS
  technology from Berkeley Predictive Technology
  Model (BPTM) and simulated using HSPICE
• Nominal Case Vdd 1V, Vtn 0.2 V , Vtp
  -0.22 V and Temp 25C.
• Worst Case Leakage Vdd 1V, Vtn 0.15 V,
  Vtp -0.1502 V and Temp 110C.
• Bitline parasitics modeled as a 5-p network for a
  group of 32 cells
• Voltage-mode sense amplifiers fired after an
  input offset of 50mV and current-mode sense
  amplifiers fired after an input offset of 20 µA

R.K.Grube et al., Design limitations in deep
sub-0.1um CMOS sram, Great Lakes Symposium on
VLSI, 2002, pp.94-97
30
Simulation Methodology

• Run simulations without enabling the sense
  amplifier
• Determine time to fire the sense amplifier
• When bit-line differential is developed
• Re-run simulations with the appropriate sense
  enable (SAen) signal
• Perform the above steps with
• Worst case leakage conditions
• BLC circuit under worst case leakage conditions

31
Impact of Variations on C2IL

• Intra-die variations that lead to worst case
  delay
• Assume BL stays high and BL going low
• Reduced Leff and Vt for the highlighted devices
• Delayed offset voltage at the input nodes

32
RESULTS Impact of Variations on C2IL

• 10 mismatch in Leff and Vt causes 20 increase
  in the delay
• Idsat kn (W/Leff)(Vgs-Vt)2/2
• Circuit malfunctions for more than 12 variation

33
RESULTS Effect of Bit-line Capacitance

• Current sense amplifiers perform better
• MDCSA performs better than all others
• Alpha latch performs better than C2IL for longer
  columns

Total Delay (WL to SAout) vs. No. of Cells Per
Column of Bit-line
34
RESULTS Effect of Bitline Leakage

• Leakage affects performance significantly for
  all sense amplifiers
• MDCSAs performance degrades with bitline
  leakage
• CBLSA performs better than all other sense
  amplifiers

35
RESULTSEffect of BLC Scheme

• BLC is effective in reducing the impact of
  bitline leakage
• However, not fully compensating the bitline
  leakage current

36
RESULTS ENERGY COMPARISON

• Voltage-mode provides low-energy dissipation
• Current-mode dissipates more energy
• CBLSA pulls down the bitlines
• MDCSA has more direct path currents
• Leakage conditions affect energy consumption by 3
  times

37
Proposed Work

• Same experiments on two other sense amplifiers
• Izumikawa Current Sense Amplifer
• Charge-Transfer Sense Amplifier Manoj 02
• Effect of variations on the delay of all sense
  amplifiers
• Variations in Vdd and Temperature
• Effect of mismatch in each device on the
  performance
• Experiments on two different number of cells per
  column namely 32 and 64
• Different components of energy dissipation
• Energy dissipated in bitlines, sense Amplifier
  and due to leakage

38
Time Line
39
Conclusion

• Voltage-mode sense amplifiers performance
  degrades with increasing bitline capacitance
• Current-mode perform better than voltage-mode for
  nominal case with increasing bitline capacitance
• Leakage affects performance significantly for all
  sense amplifiers
• MDCSA is affected the most due to the performance
  degradation of the current transporting unit (SFT
  circuit)
• Bitline leakage compensation is effective
• Does not fully compensate the leakage current
• Impact of variations on the delay of the C2IL
  sense amplifier is significant

40
References

• 1 A. Chandrakasan et. al., Design of
  High-Performance Microprocessor Circuits, IEEE
  Press 2001.
• 2 E. Seevinck et. al. , Current Mode
  Techniques for High-Speed VLSI Circuits with
  Application to Current Mode Techniques for High
  Speed VLSI Circuits with Application to Current
  Sense Amplifier for CMOS SRAMs. , IEEE JSSC,
  pp. 525-535, 1991.
• 3 K.Agawa et. al. , A Bitline Leakage
  Compensation Scheme for Low- Voltage SRAMs.,
  IEEE JSSC, pp. 726-734, 2001.
• 4 M. Sinha, Low-Voltage Sensing Techniques for
  High-Speed On-chip Global Interconnects and
  Caches. , MS Thesis, ICDG, University Of
  Massachusetts Amherst.
• 5 Y.Ye et. al. , A 6 Ghz 16 Kbytes L1 cache in
  a 100nm dual Vt technology using a bitline
  leakage reduction (BLR) technique, Symposium on
  VLSI Circuits digest of technical papers, pp.
  50-51, 2002.
• 6 T. N. Blalock, and Richard C. Jaeger, "A
  High- Speed Clamped Bit-Line Curent-Mode Sense
  Amplifier," IEEE JSSC, pp. 542-548, 1991.
• 7 Jan M. Rabaey, Digital Integrated Circuits
  A design Perspective , Prentice Hall 1996.