Jaeger/Blalock

1
Chapter 16Analog Integrated Circuits

• Microelectronic Circuit Design
• Richard C. Jaeger
• Travis N. Blalock

Chap 16 - 1
2
Chapter Goals

• Understand bipolar and MOS current mirror
  operation and mirror ratio errors.
• Explore high output resistance current sources
  including cascode and Wilson current sources.
• Design current sources for both discrete and
  integrated applications.
• Study reference current circuits such as
  VBE-based reference, bandgap reference and Widlar
  current source.
• Use current mirrors as active loads in
  differential amplifiers to increase voltage gain
  of single-stage amplifiers.
• Study effects of device mismatch on amplifier
  performance.
• Analyze design of classic mA741 op amp.
• Study realization of four-quadrant analog
  multipliers with large input signal range.
• Increase understanding of SPICE simulation
  techniques.

Chap 16 - 2
3
MOS Current Mirrors DC Analysis
However, due to mismatches, VDS1 is not equal to
VDS2 and there is slight mismatch between output
and reference currents. Mirror ratio is
MOSFETs M1 and M2 are assumed to have identical
VTN, Kn, l, and W/L ratios. IREF provides
operating bias to mirror. VDS1 VGS1 VGS2 VGS
Chap 16 - 3
4
MOS Current Mirror (Example)

• ProblemCalculate output current for given
  current mirror.
• Given data IREF 150 mA, VSS 10 V, VTN 1
  V, Kn 250 mA/V2, l 0.0133 V-1
• Analysis (1 l VDS1) term is neglected to
  simplify dc bias calculation.

Actual currents are found to be mismatched by
approximately 10.
Chap 16 - 4
5
MOS Current Mirrors Changing Mirror Ratio
Mirror ratio can be changed by modifying W/L
ratios of the two transistors forming the mirror.
In given current mirror, Io 5IREF. Again
mismatch in VDS causes error in MR.
Chap 16 - 5
6
Bipolar Current Mirrors DC Analysis
BJTs Q1 and Q2 are assumed to have identical IS,
VA, bFO, and W/L ratios. Io IC2, IREF
IC1 IB1 IB2 VBE1 VBE2 VBE
Finite current gain of BJT causes slight mismatch
between Io and IREF.
Chap 16 - 6
7
Current Mirror (Example)

• ProblemCalculate and compare mirror ratios for
  BJT and MOS current mirror.
• Given data IREF 150 mA, VGS 2 V, VDS2
  VCE2 10 V, l 0.02 V-1 VA 50 V, bFO 100,
  VSS 10 V, M1 M2, Q1 Q2.
• Analysis

Chap 16 - 7
8
Bipolar Current Mirrors Changing Mirror Ratio
Emitter area scaling changes the transport
equations using which, Ideally, MR n, but for
finite gain,
Mirror ratio can be changed by modifying the
emitter area of the transistor.
Chap 16 - 8
9
Multiple Current Sources

• Reference current enters diode-connected
  transistor M1 establishing gate-source voltage to
  bias M2 through M5, each with different W/L
  ratio.
• Absence of current gain defect permits large
  number of MOSFETs to be driven by one reference
  transistor.
• Similar multiple bipolar sources can be built
  from one reference BJT.
• As base current error term worsens when more BJTs
  are added, umber of outputs of basic bipolar
  mirror are limited.

Chap 16 - 9
10
Buffered Bipolar Current Mirror
Assuming infinite Early voltage for simplicity,
When large mirror ratio is used or if many source
currents are generated from one reference BJT,
current gain defect worsens. Current gain of Q3
is used to reduce base current that is subtracted
from reference current.
Thus error term in denominator is reduced.
Chap 16 - 10
11
Output Resistance of Current Mirrors
This simplifies the ac model of the current
mirror. Similar analysis applies to MOSFET
current mirror except that the current gain is
infinite. Thus or
For diode connected BJT, from small-signal model,
...If boand mF gtgt1
Chap 16 - 11
12
Two-port Model for Current Mirror
Since current mirror has a current input and
current output, we use h-parameters.
For MOS current mirrors,
Chap 16 - 12
13
Bipolar Widlar Current Source
Current through R is given by If transistors
are matched, Typically 1 lt K lt 10.
R in Widlar source allows adjustment of mirror
ratio.
Chap 16 - 13
14
PTAT Voltage

• Voltage developed across R in Widlar current
  source is directly proportional to absolute
  temperature.
• Example T 300 K, IC1 IC2 and AE2 10 AE1.
  Then 59.6 mV with temperature coefficient of
  slightlylt 0.2 mV/K
• PTAT voltage combined with A-D converter is the
  core of electronic thermometers.

Chap 16 - 14
15
MOS Widlar Current Source
If IO is known, IREF can be directly calculated.
If IREF , R and W/L ratios are known, we can
write a quadratic equation in terms
of Small-signal model for MOS Widlar source
represents a C-S stage with resistor R in its
source.
Current through R is given by
Chap 16 - 15
16
MOS Wilson Current Source
where
From small-signal model,
During operation, all transistors are in active
region. ID2 IREF , ID3 ID1 IO, VGS3
VGS1VGS
Chap 16 - 16
17
Bipolar Wilson Current Source
Addition of extra BJT can balance the circuit and
reduce errors due to mismatch.
During operation, all transistors are in active
region. But some current is lost at base of Q3
and current gain error is formed by Q1 and
Q2. IREF IC2 IB3 VCE1 VBE
VCE2 2VBE
VCE2 VBEVBE3 -VBE4 VBE
Chap 16 - 17
18
MOS Cascode Current Source
ID1 ID3 IREF Also IO ID4 ID2. So current
mirror forces output current to be approximately
equal to the reference current. If all
transistors are matched with equal W/L
ratios, VDS2 VGS1 VGS3 -VGS4 VGS VDS1
From the small-signal model,
Chap 16 - 18
19
Bipolar Cascode Current Source
IC1 IC3 IREF Also IO IC4 IC2. So current
mirror forces output current to be approximately
equal to the reference current. If all
transistors are matched, VCE2 VBE1 VBE3 -VBE4
VGS VCE1
From the small-signal model,
Chap 16 - 19
20
Electronic Current Source Design Example

• Problem Design IC current source to meet given
  specifications.
• Given data IREF 25 mA, VSS 20 V, l 0.02
  V-1 , VTN 0.75 V, Kn 50 mA/V2, VA 50 V,
  bFO 100, ISO 0.5 fA
• Analysis MR lt0.1 requires output current of 25
  mA25 nA when output voltage is 20 V.
  Choose 1GW for safety
  margin.
• 
  
• Cascode or Wilson sources voltage-balanced
  MOS version must be used to meet this value of
  VCS and for small MR. We can choose cascode
  source as it doesnt involve internal feedback
  loop.W/L ratios are all same as MR1.
• Using mf 500, l 0.02/V and ID 25 mA gives
  value of Kn1.25 mS. Since Kn Kn(W/L) we need
  a W/L ratio of 25/1 for given technology.

Chap 16 - 20
21
Reference Current Generation

• Reference current is required by all current
  mirrors.
• When resistor is used, sources output current is
  directly proportional to VEE.
• Gate-source voltages of MOSFETs can be large and
  several MOS devices can be connected in series
  between supplies to eliminate large resistors.
• VDD VSS VSG4 VGS3 VGS1 and ID3
  ID1 I4
• Change in supply directly alters gate-source
  voltage of MOSFETs and the reference current.
• BJTs cant similarly be connected in series due
  to small fixed voltage developed across each
  diode and exponential relation between voltage
  and current.

Chap 16 - 21
22
Supply-Independent Biasing JFET Constant
Reference Current Source

• P-channel JFETs can be used to set a fixed
  reference current.
• JFET is operating with VSG0 and thus ID IDSS,
  assuming that VSD is large enough to pinch-off
  the JFET.
• Depletion-mode MOSFETs can be used in similar
  manner.
• Since both these methods require special IC
  processes, other methods are preferred.

Chap 16 - 22
23
Supply-Independent Biasing VBE -based Reference
and Widlar Current Source
Output current is now logarithmically dependent
on supply voltage. However, it is temperature
dependent due to temperature coefficients of both
VBE and R. Widlar source also achieves similar
supply independence of output current.

• Output current is determined by base-emitter
  voltage of Q1 . For high current gain,

Chap 16 - 23
24
Supply-Independent Biasing Bias Cell Using
Widlar Source and Current Mirror
Actual value of output current depends on
temperature and absolute value of R. IC1 IC2 0
is also a stable operating point and start-up
circuits must be included in IC realizations to
ensure that circuit reaches desires operating
point. Base-emitter voltages of Q1 and Q4 can be
used as reference voltages for other current
mirrors. In MOS analog of the circuit,
ID3 ID4 and so ID1 ID2.
Assuming high current gain, pnp current mirror
forces IC1 IC2. Emitter area ratio for Widlar
source is shown to be 20.
Chap 16 - 24
25
Variation of Reference Cell Current with Power
Supply Fluctuations
or
Using Determinant of these nodal equations is
R is absorbed into transistor model in simplified
small-signal circuit model.
Chap 16 - 25
26
Variation of Reference Cell Current with Power
Supply Fluctuations (contd.)
for .This is important for
stability. Because of positive feedback, overall
output resistance is reduced.
Output resistances of the Widlar source and
current mirror, ro2 and ro3 determine
sensitivity to power supply variations. To
improve output resistance of Widlar portion ,
cascode sources can be used and Wilson sources
can be used to improve output resistance of
current mirror.
Chap 16 - 26
27
Reference Current Design Example

• Problem Design supply-independent current source
  to meet given specifications.
• Given data output current 45 mA,T300 K, total
  currentlt 60 mA VCC VEE 5 V, VA 75 V, bFO
  100, ISO 0.1 fA, VT 25.88 mV
• Analysis
• Also . Choose IC25 IC1.
  Then AE2/ AE1 lt28.45 Choosing
• AE2/AE1 20,
• Finally, AE1A, AE220 A, AE3A, AE45 A with
  35.88 mV across R.

Chap 16 - 27
28
Bandgap Reference
To have zero temperature
coefficient, VGO is silicon
bandgap voltage at 0K (1.12 V)
To make the voltage reference temperature
independent, negative temperature coefficient of
base-emitter junction can be canceled by positive
temperature coefficient of scaled PTAT voltage.
Chap 16 - 28
29
Bandgap Reference Circuit Realization
Voltages other than 1.2 V can be obtained by a
adding resistive voltage divider.
Circuit gain G 2 R2 / R1.
Chap 16 - 29
30
Bandgap Reference Example

• Problem Design bandgap reference to meet given
  specifications.
• Given data VO 5 V,T320 K, collector current
  25 mA, IS 0.5 fA.
• Assumptions VA is infinite, bFO is infinite, AE2
  10 AE1, drop across R 2 V.
• Analysis

Chap 16 - 30
31
CMOS Differential Amplifier with Active Load DC
Analysis
ID3 ID1 ID2 ID4 IDSS/2. Mirror ratio is set
by M3 and M4 and is exactly unity when VSD4
VSD3 and thus VSD1 VSD2. Differential amplifier
is completely balanced at dc when
Chap 16 - 31
32
CMOS Differential Amplifier with Active Load
Differential-Mode Signal Analysis
Thevenin equivalent output resistance Differenti
al-mode voltage gain
The differential amplifier can be represented by
its Norton equivalent. Total short circuit output
current
Chap 16 - 32
33
CMOS Differential Amplifier with Active Load
Output Resistance
Drain current of M2 (vx/2ro2)is replicated by
current mirror as drain current of M4. Total
current from source is 2(vx/2ro2) vx/ro2. Total
current is Output resistance is
Assume RSS gtgt1/ gm1. Resistance looking into
drain of M2 (C-G transistor) is
Chap 16 - 33
34
CMOS Differential Amplifier with Active Load
Common-Mode Signal Analysis
From small-signal equivalent where it is
assumed that gm4 gm3 and Goc ltlt gm3. Also
Chap 16 - 34
35
CMOS Differential Amplifier with Active Load
CMRR and Mismatch Contribution
for ro3 ro2.
With mismatched transistors, assuming vd10 and
gate-source voltages are equal, With vgs vic-
vs, vd10 and vd20,
Chap 16 - 35
36
Bipolar Differential Amplifier with Active Load
DC Analysis
Differential amplifier is completely balanced at
dc when Current gain defect in current mirror
upsets dc balance. As longs as BJTs are in
forward-active region, VEC4 adjusts to make up
for current-gain defect. As IC2 IC4 and
IC2
IC1, MR
must be 1.
IC3 IC1 IC2 IC4 IEE/2. If bFO is very
large, current mirror ratio is set by Q3 and Q4
and is exactly 1 when VEC4 VEC3VEB.
This causes an equivalent input offset voltage of
Chap 16 - 36
37
Bipolar Differential Amplifier with Active Load
Differential-Mode Signal Analysis
Thevenin
equivalent
output resistance Differential-mode voltage
gain
With added stages, output resistance of
differential input stage is
To eliminate offset error, buffered current
mirror active load is used. Total short circuit
output current
Chap 16 - 37
38
Bipolar Differential Amplifier with Active Load
Common-Mode Signal Analysis

Current forced in differential output resistance
is doubled due to current mirror action.
Due to mismatches,
From small-signal equivalent
Chap 16 - 38
39
Active Loads in Op Amps Voltage Gain
If Wilson stage is used in first-stage active
load, Avt1 mf2. If current source M10 is
replaced by a Wilson or cascode source, Avt2
mf5.Overall gain can be raised to
Gain of output stage is approximately 1.
Chap 16 - 39
40
Active Loads in Op Amps DC Design Considerations

• When op amp with active load is operated in
  closed-loop configuration, ID5 I2, the output
  current of source M10.
• For minimum offset voltage, (W/L)5 must be such
  that VSG5 VSD4 VSG3 precisely sets ID5 I2
  and accounts for VDS and l differences between M5
  and M10.
• RGG, (W/L)6 and (W/L)7 determine quiescent
  current in class-AB output stage.
• VGS11 can be used to bias output stage in place
  of RGG.

Chap 16 - 40
41
CMOS Op Amp Analysis

• Problem Find small-signal characteristics of
  given CMOS op amp.
• Given data IREF 100 mA, VDD VSS 5 V, VTN
  1 V, VTP -0.75 V, Kn 25 mA/V2, Kp 10
  mA/V2, l 0.0125 V-1
• Analysis

As ID6 ID7, VGS6 VSG7 VGS11 /2
Chap 16 - 41
42
Bipolar Op Amps

• Load resistance is driven by class-AB output
  stage formed by Q6 and Q7 , biased by I2 and
  diodes Q11 and Q12.

• Q1 to Q4 form differential input stage with
  active load.
• First stage is followed by high-gain C-E
  amplifier, Q5 and its current source load, Q8.

Chap 16 - 42
43
Bipolar Op Amps with Improved Voltage Gain
Buffered current mirror maintains dc balance at
collectors of Q3 and Q4.
Using I2 2 I1, bo50, VA60 V, VCE 15 V,
To improve gain, 2-transistor Darlington circuit
with current gain of bo1bo2, amplification factor
mf2 /4, output resistance ro2 /2 and input
resistance 2bo1 rp2,is used to replace Q5. It
requires emitter-base bias of 2VEB.
Chap 16 - 43
44
Input Stage Breakdown in Bipolar Op Amps
Early IC op amps used external diode protection
across input terminals to limit differential
input voltage to about 1.4 V at the cost of extra
components.

• Input stage of bipolar op amp has no overvoltage
  protection and can easily be destroyed by large
  input voltage differences due to fault conditions
  or unavoidable transients, such as slew-rate
  limited recovery.
• In worst-case fault condition, B-E junction of Q1
  is forward-biased and that of Q2 is
  reverse-biased by(VCC VEE - VBE1). If VCC VEE
  22 V, reverse voltage gt 41 V.

Chap 16 - 44
45
mA741 Op Amp

• High gain, input resistance and CMRR, low output
  resistance and good frequency response.
• Fully protected input and output stages and
  offset adjustment port.
• Input stage is a differential amplifier with
  buffered current mirror active load.
• Two stages of voltage gain (emitter-follower
  driving C-E amplifier) followed by short-circuit
  protected class-AB output stage buffered from
  second gain stage by emitter follower.

Chap 16 - 45
46
mA741 Op Amp Bias Circuitry
Assuming VO 0, VCC 15 V and neglecting drop
across R7 and R8 , VEC23 151.416.4 V and
VEC24 15-0.7 14.3 V Given VA60 V, bFO 50,
Solving iteratively, I1 18.4 mA.
Chap 16 - 46
47
mA741 Op AmpDC Analysis of Input Stage
Chap 16 - 47
48
mA741 Op Amp Input Stage Bias Currents Example

• Problem Calculate bias currents in the 741 input
  stage with given parameters.
• Given data I1 18 mA,VCC VEE 15 V, VAnpn
  75 V, bFOnpn 150, VApnp 60 V, bFOpnp 60
• Analysis

Chap 16 - 48
49
mA741 Op Amp AC Analysis of Input Stage
Using symmetry of the input stage
differential-mode half circuit can be drawn.
Chap 16 - 49
50
mA741 Op Amp Voltage Gain (Input Stage)
Based on values in Norton equivalent,
open-circuit voltage gain of first stage is -955.
Chap 16 - 50
51
mA741 Op Amp Voltage Gain (Second Stage)
To find y11 and y21
Chap 16 - 51
52
mA741 Op Amp Voltage Gain (Second Stage contd.)
To find y12 and y22 Open-circuit voltage
gain for the first two stages is
Combined model for first and second stages is
Chap 16 - 52
53
mA741 Op Amp Voltage Gain (Output Stage)
From simplified output stage without
short-circuit protection
Actual op amp output resistance is
Chap 16 - 53
54
Gilbert Analog Multiplier
Multiplication can be achieved by expanding the
tanh as a series and keeping only first
term. But this restricts input signal range of
v2 to only a few tens of mV.

Q1 and Q2 have significant emitter degeneration,
transconductance of the pair is 1/ R1.For v1 lt
R1IBB,
Chap 16 - 54
55
Four-Quadrant Gilbert Analog Multiplier with
Predistortion Circuit
For v3 lt R3IEE,
Chap 16 - 55