Computer Arithmetic, Kmaps

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Computer Arithmetic, K-maps
Lecture 5

• Prof. Sin-Min Lee
• Department of Computer Science

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Bit-Serial and Ripple-Carry Adders
Half-adder (HA) Truth table and block diagram
Full-adder (FA) Truth table and block diagram
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Half-Adder Implementations
Three implementations of a half-adder.
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Full-Adder Implementations
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Radix Conversion Old-Radix Arithmetic
Converting whole part w (105)ten
(?)five Repeatedly divide by five Quotient Remain
der 105 0 21 1
4 4 0 Therefore, (105)ten
(410)five
Converting fractional part v (105.486)ten
(410.?)five Repeatedly multiply by five Whole
Part Fraction .486 2
.430 2 .150 0
.750 3 .750 3
.750 Therefore, (105.486)ten ?
(410.22033)five
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Radix Conversion New-Radix Arithmetic
Converting whole part w (22033)five (?)ten
((((2 ? 5) 2) ? 5 0) ? 5 3) ? 5 3
-----
10
-----------
12
---------------------
60
-------------------------------
303
-----------------------------------------
1518
Converting fractional part v (410.22033)five
(105.?)ten (0.22033)five ? 55 (22033)five
(1518)ten 1518 / 55 1518 / 3125
0.48576 Therefore, (410.22033)five
(105.48576)ten Horners rule is also
applicable Proceed from right to left and use
division instead of multiplication
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Horners Rule for Fractions
Converting fractional part v (0.22033)five
(?)ten (((((3 / 5) 3) / 5 0) / 5 2)
/ 5 2) / 5 -----
0.6
-----------
3.6
---------------------
0.72
-------------------------------
2.144
-----------------------------------------
2.4288
----------------------------------------------
- 0.48576
Horners rule used to convert (0.220 33)five to
decimal
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Signed-Magnitude Representation
Four-bit signed-magnitude number representation
system for integers
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Twos- and 1s-Complement Numbers
Twos complement radix complement system for r
2 M 2k 2k x (2k ulp) x
ulp xcompl ulp Range
of representable numbers in with k whole bits
from 2k1 to 2k1 ulp
A 4-bit 2s-complement number representation
system for integers.
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Why 2s-Complement Is the Universal Choice
Adder/subtractor architecture for 2s-complement
numbers.
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Signed-Magnitude vs 2s-Complement
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Truth table to K-Map
minterms are represented by a 1 in the
corresponding location in the K map.
The expression is A.B A.B A.B
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K-Maps

• Adjacent 1s can be paired off
• Any variable which is both a 1 and a zero in this
  pairing can be eliminated
• Pairs may be adjacent horizontally or vertically

a pair
B is eliminated, leaving A as the term
another pair
A is eliminated, leaving B as the term
The expression becomes A B
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• Two Variable K-Map

A.B.C A.B.C A.B.C
One square filled in for each minterm.
Notice the code sequence 00 01 11 10 a Gray
code.
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Grouping the Pairs
equates to B.C as A is eliminated.
Here, we can wrap around and this pair equates
to A.C as B is eliminated.
Our truth table simplifies to A.C B.C as
before.
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Groups of 4
Groups of 4 in a block can be used to eliminate
two variables
The solution is B because it is a 1 over the
whole block (vertical pairs) BC BC B(C C)
B.
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Karnaugh Maps

• Three Variable K-Map
• Extreme ends of same row considered adjacent

A BC
00
01
11
10
0
1
10
00
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Karnaugh Maps

• Three Variable K-Map example

A BC
00
01
11
10
0
1
X
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The Block of 4, again
A BC
00
01
11
10
0
1
1
1
1
1
X C
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Returning to our car example, once more

• Two Variable K-Map

A.B.C A.B.C A.B.C
There is more than one way to label the axes of
the K-Map, some views lead to groupings which are
easier to see.
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Karnaugh Maps

• Four Variable K-Map
• Four corners adjacent

AB CD
00
01
11
10
00
01
11
10
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Karnaugh Maps

• Four Variable K-Map example

AB CD
00
01
11
10
00
01
11
10
F
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Product-of-Sums
We have populated the maps with 1s using
sum-of-products extracted from the truth
table. We can equally well work with the 0s
P (A B).(A C) P A.B A.C
equivalent
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Inverted K Maps

• In some cases a better simplification can be
  obtained if the inverse of the output is
  considered
• i.e. group the zeros instead of the ones
• particularly when the number and patterns of
  zeros is simpler than the ones

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Karnaugh Maps

• Example Z5 of the Seven Segment Display

X1 X2 X3 X4 Z5
0 1 2 3 4 5 6 7 8 9
0 0 0 0 1
0 0 0 1 0
X1X2 X3 X4
00
01
11
10
0 0 1 0 1
0 0 1 1 0
00
0 1 0 0 0
01
0 1 0 1 0
11
0 1 1 0 1
0 1 1 1 0
10
1 0 0 0 1
1 0 0 1 0
Z5
1 0 1 0 X
1 0 1 1 X

• Better to group 1s or 0s?

1 1 0 0 X 1 1 0 1 X 1 1 1 0 X 1 1 1 1 X
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Example Majority Function

• Three inputs A, B, C
• One output M
• Output takes truth value of majority inputs. I.e.
• M is 1 iff two of A,B,C is 1
• M is 0 iff two of A, B, C is 0
• Notice writing large truth tables is cumbersome

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Alternative Representation

• Collect the combinations of variable that give 1
  for output.
• Write the function as a SUM of these terms
• In terms, write variable name for value 1, and a
  bar over the name for 0.
• EG M ABCABCABCABC

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Rationale for New Notation

• Consider ABC The product is for AND
• Consider ABCABC The sum is for OR
• So we are writing the function as a sum of
  products
• I.e. AND-ing OR-terms Called conjunctive normal
  form.
• Consider ABC This is 1 iff A0, B1 and C1
• A function of N variables can be given as sum of
  2N n-variable products

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Creating Circuits for Boolean Functions

• MABCABCABCABC
• 1,2,3 are NOT gates feeding lines A,B,C
• 4,5,6,7 are AND gates corresponding to the four
  product terms
• 8 is an OR term corresponding to the sum
• A,B,C have been inserted to avoid clutter they
  could be connected directly out of NOT gate

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Implementing Boolean Functions

• Write the truth table
• Provide inverters for complementing inputs
• Draw an AND gate for each term with 1in output
  column
• Wire the AND gates to appropriate inputs
• Feed the outputs of all AND gates into an OR gate

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Using A Single Gate Type

• It is desirable to use only one type of gate
  generate the whole circuit.
• Can use NAND or NOR gate.
• In order to do so, enough to show that
• NOT, AND, OR NAND can be generated by NOR gates
• NOT, AND, OR, NOR ca be generated by NAND gates.
• We say that NAND, NOR are complete for Boolean
  circuits

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Completeness of NAND
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Completeness of NOR
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Circuit Equivalence

• Sometimes need to minimize number of elements on
  a board
• get minimum number of gates
• Two input gates instead of four input gates
• Need to find an equivalent circuit for the given
  circuit
• Equivalent having same input output behavior
  computing same Boolean function
• Use Boolean Algebra

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Example Using ABAC A(BC)
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Some Laws of Boolean Algebra
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Consequences of De Morgans Law
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Using De Morgans Laws to covert sum of products
to NAND
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De Morgan again

• A NAND gate
• Y A.B A B
• is the same as an OR gate with two NOT gates
• Similarly a NOR gate is the same as an AND gate
  with two inverters
• Y A B A.B
• not the individual terms
• change the sign
• not the lot

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Dual gates
not the individual inputs change the gate not the
output
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Truth Tables and Boolean Notation

• NAND Gate Representation
• It is possible to implement any boolean
  expression using only NAND gates

NOT
X
X
AND
A.B
A
A.B
B
OR
A
AB
B
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Truth Tables and Boolean Notation

• NAND Gate representation
• Implement the following circuit using only NAND
  gates

x2
x4
x3
De Morgan can also be represented visually
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Exercise

• Implement NOT, AND and OR using NOR gates
• Example AND gate dual
  circuit

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Solution

• Similar pattern to using NAND gates (not
  surprising)
• NOT
• AND
• OR

X
X
A.B
A
A
A.B
B
A.B
B
A
AB
A.B
A
AB
B
B
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Truth Tables and Boolean Notation

• NOR Gate representation
• It is also possible to implement any boolean
  expression using only NOR gates
• Implement the following circuit using only NOR
  gates

X4
X3
X
2
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Solution

• Two NOR gates in sequence acting as NOTs can be
  eliminated

X4
X3
X
2
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