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END OF LIFE FOR SI: CMOL CIRCUIT ARCHITECTURES

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END OF LIFE FOR SI: CMOL CIRCUIT ARCHITECTURES. EN 291 NANOSYSTEM ... x,y--- horizontal,vertical coordinate of each cell. f--- empirically selected exponent ... – PowerPoint PPT presentation

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Title: END OF LIFE FOR SI: CMOL CIRCUIT ARCHITECTURES


1
END OF LIFE FOR SICMOL CIRCUIT ARCHITECTURES
  • EN 291 NANOSYSTEM DESIGN
  • Elif Alpaslan

BROWN UNIVERSITY FALL2005
2
OUTLINE
  • Impending crisis of microelectronics
  • Basic idea behind CMOL circuits
  • Structure of the hybrid CMOS/nanowire/nanodevice
    circuits
  • Advantages of the CMOL circuits compared to other
    structures
  • Applications of CMOL circuits

3
WHY A NEED FOR NEW TECHNOLOGIES??
  • MOORE'S LAW
  • The number of transistors that can be integrated
    on single die would grow exponentially with time
    (1960)

4
EVALUATION IN COMPLEXITY
5
CURRENT VLSI PARADIGM
  • Combination of
  • Lithographic patterning
  • CMOS circuits
  • Boolean logic
  • Solution shift from lithography-based
    fabrication to the bottom-up approach based on
    nanodevices
  • What about the functionality of nanodevices??
  • Needs to be added to CMOS subsystem
  • Hybrid CMOS/nanodevice circuits
  • Application areas
  • digital memories,reconfigurable boolean
    logic,mixed-signal neuromorphic networks

Can't be extended into few-nm-region
6
IDEA BEHIND CMOL CIRCUITS
  • Advantages of CMOS
  • Flexibility
  • High fabrication yield
  • Standard fabrication --gt lower cost
  • Advantages of nanodevices
  • Small
  • High potential density of molecular scale
  • WHY NOT TO COMBINE ??

7
DUBBED CMOL
  • Structure of a generic CMOL circuit
  • How this type of an interface different from what
    we have seen as now?

8
PIN PLACEMENT AND ADRESSING
  • pin arrangement as square array with each side
    2ßFCMOS
  • FCMOS half pitch of CMOS subsystem
  • FNANO half pitch of nanowires
  • ß dimensionless factor
  • a nanowire crossbar angle arcsin(FNANO/FCMOS)

9
ACCESSING NANODEVICES
  • I-V Curve shows that the device may be switched
    between two internal states(ON-OFF) by applying
    -Vw or Vw
  • So applying -2Vw or 2Vw to the selected
    nanodevice exceeds the corresponding switching
    threshold,while half selected devices are not
    disturbed.

10
ADVANTAGES OF CMOL CIRCUITS
  • Nanowire formation of advanced patterning
    techniques with lack of precise alignment is
    allowed
  • WHY?
  • Fabrication and self-assembly is less challenging
  • WHY?

11
DISADVANTAGES OF CMOL CIRCUITS
  • Defect tolerant circuit architectures is required
  • WHY?
  • Compare this issue for semiconductor
    transistors!!!

12
APPLICATIONS OF CMOL CIRCUITS
  • CMOL MEMORIES
  • A straightforward potential application because
    of the simple structures of memories
  • Nanodevice ----------gt single bit memory cell
  • CMOS subsystem -------gt coding,decoding,sense
    amplifier,line driving

13
DEALING WITH DEFECT TOLERANCE
  • TWO TECHNIQUES
  • Memory reconfiguration
  • Replace several rows and columns with largest
    number of bad memory cells
  • Error correction
  • Based on Hamming code

14
OPTIMIZED TOTAL CHIP AREA PER USEFUL BIT
NANODEVICE YIELD
  • Compare CMOS memories and hybrid CMOL memories
    from below graph.
  • Are this results optimistic??

15
CMOL FPGA BOOLEAN LOGIC CIRCUITS
  • Reconfiguration very important technique for
    dealing with defective nanodevices in hybrid
    circuits.
  • FPGA based CMOL-hybrid structures important
  • HOW AN FPGA WORK? Very shortly
  • LUTS
  • PLA
  • Alternative approach to reconfigurable
    architecture for hybrid CMOS/nanodevice circuits

16
ARCITECTURE
  • For FPGA applications
  • a45
  • CMOS cell area
  • Asquare(2ßFCMOS)
  • Input -output of a CMOS cell connection
  • pin-nanowire-nanodevice-nanowire-pin

17
CMOS CELLS
  • Two pass transistors, an inverter which are
    connected to nanowire/nanodevice subsystem via
    two pins

18
PRINCIPLE
  • Configuration Stage disable all inverters and
    test set all nanodevices
  • Pass transistors are used as pull down resistors
    while nanodevices set ON state and used as pull
    up resistors
  • a primitive implementation of a Boolean function
  • Example wired NOR gate (on table)

19
RECONFIGURATION
  • For increasing the fabrication yield
    reconfiguration of an integrated circuit around
    bad devices becomes very important
  • Reconfigurable computer architectures allow one
    to locate bad components first an then implement
    optimum reconfiguration of the system leading
    high defect tolerance
  • e.g Teramac computer

20
RECONFIGURATION ALGORITHMS
  • Different algorithms for reconfiguration of the
    CMOL FPGAs
  • Quasi-optimal
  • Exhaustive-search
  • Simple linear time algorithm
  • First stage map circuit on defect free CMOL
    fabric (CAD tools are required)
  • Second stage reconfigure around defective
    components

impractible
21
AFTER MAPPING
  • Assumptions
  • one defect type
  • absence of nanodevices at certain crosspoints
    (stuck open fault)
  • defects are randomly distributed
  • Algorithm
  • Each gate from a cell is moved with bad
    input/output connection to a new cell while
    keeping input/output gates in fixed positions
  • Why such an algorithm?

22
IMPLEMENTING THE ALGORITHM
  • Repair region overlap of connectivity domains of
    all inputs and outputs of a gate
  • a gate can be moved if there are no other cells
    in repair region

Condition for swapping A and B
23
What if there are several positions for a gate
swap?
  • Prioritize each position based on providing
    smaller interconnect length
  • For each position calculate
  • list of all possible moving options in the order
    of increasing F, for defective interconnects
  • Reconfiguration failureno possible moving option
    with good connections
  • Analysis of this reconfiguration algorithm most
    reconfiguration failures come from longest
    interconnections

x,y---gt horizontal,vertical coordinate of each
cell f---gt empirically selected exponent
24
KOGGE -STONE ADDER
  • Integer parallel-prefix adder
  • Most regular adder structure ---gt easily mapped
    into CMOL FPGA fabric

25
KOGGE-STONE ADDER
  • Conversion into fan-in-two NOR gate netlist
  • Conversion into fan-in-two NOR gate netlist

26
FROM NOR GATE NETLIST INTO CMOL BLOCK
  • Mapping into rectangular CMOL block
  • connectivity domain radius r'10
  • connectivity domain's diagonal cells
    2(r'-1)18 cells
  • logic depth21

27
LOGIC DEPTH VS r'
  • Logic depth number of logic levels in the
    critical path

smaller r' ----gtlarger logic depth -----gtlarger
number of CMOS cells _at_ r'rmin --------gt layout
impossible
28
KOGGE-STONE ADDER
  • Reconfiguration results
  • After initial mapping ---gtpoor defect tolerance
  • After reconfiguration Kogge Stone Adder looks like

29
COMPARE THE RESULTS
  • Before reconfiguration
  • Poor defect tolerance
  • Yield goes down very rapidly
  • q bad nanodevice fraction is low (5x(10)-5)
  • After reconfiguration
  • q increased dramatically q0.5

Layout of a part of the circuit with showing
defective nanodevices
30
FULL CROSSBAR
  • Second case study
  • A fully connected crossbar
  • a) general configuration of CMOL circuit
  • b) assigning each pair by using greedy algorithm
  • c) path creation for the I/O pairs
  • Allocation of the cells

m vertical size of the array n horizontal
size of the array
31
ROUTING ALGOTIRHM
  • Selecting vertical size (m) of array?
  • Smallest value for m
  • WHY?
  • Calculation of the min m.
  • mmin n/(r'-2)2
  • Logic depth calculation
  • d(nm)/(r'-2)

32
COMPARISON OF TWO CASES
  • same reconfiguration algorithm for two cases
  • Crossbar is less defect tolerant than adder
  • Any guess why?
  • As (r-r') increases defect tolerance of crossbar
    becomes better than adder
  • Any guess why?

33
PERFORMANCE
  • In terms of power, speed and density
  • Assumptions
  • Nanodevices
  • each switch is implemented as parallel
    connection of single electron devices
  • Min. acceptable Vdd is 0.2-0.3 V
  • Nanowires
  • specific CNANOWIRE RWIRE /L calculations

34
POWER ESTIMATIONS
  • Average total power consumption
  • Static power
  • Power due to the leakage current
  • Dynamic power

35
RESULTS
  • Power
  • Static power largest contributor
  • Delay
  • Depends on both FNANO FCMOS
  • Area
  • improved by a better CMOs subsystem

36
CMOL FPGA VS CMOS FPGA
  • For FNANO 8nm FCMOS 32nm 32 bit CMOL adder
  • Area 110 µm2 , delay1.3ns, power acceptable
  • For purely CMOS FPGA (90 nm Xilinx Spartan 3
    tech.)
  • Area 70 000 µm2 , delay5.1ns, 500 times larger
    delay product

37
CMOL CROSSNETSNEUROMORPHIC NETWORKS
  • In each CrossNet somas are implemented in CMOS
    subsystem
  • Mutually perpendicular nanowires of CMOL crossbar
    implement axons and dentries (they cary signals
    between the cells) allowing one cell to be
    connected to unlimited number M of other cells.
  • This parallelism gives flexibility to CrossNets

38
CROSSNET FUNCTIONALITY
  • Dependent on distribution of somas over
    axon/dendrite/synapse field
  • Two particular CrossNet Species
  • FlossBars layered topology
  • InBars interleaved structure

39
CONCLUSION
  • Weak conclusion (my interpretation)
  • There is a chance for development hybrid CMOL
    integrated circuits
  • Several application areas
  • Terabit scale memories
  • Reconfigurable digital circuits
  • Mixed-signal neuromorphic networks
  • Challange
  • Development of high yield techniques
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