An Experimental Investigation on the Accuracy of Stratified RTL Fault Coverage

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An Experimental Investigation on the Accuracy of
Stratified RTL Fault Coverage

• Pradip A. Thaker
• Acorn Networks, Reston, VA 20190
• (Formerly with Hughes Network Systems)
• pthaker_at_acorn-networks.com
• Vishwani D. Agrawal
• Agere Systems, Murray Hill, NJ 07974
• va_at_agere.com
• http//cm.bell-labs.com/cm/cs/who/va
• Mona E. Zaghloul
• George Washington University, Washington, D.C.
  20052
• zaghloul_at_seas.gwu.edu

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Purpose

• Follow up of the RTL fault modeling technique
  proposed at ITC 2000
• Present experimental data to demonstrate impact
  of estimation error in stratum weights on RTL
  fault coverage and error bounds

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Outline

• Background and motivation
• Previous work
• Causes of inaccuracy in stratum weights
• Stratum weight extraction techniques
• Experimental results

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Background and Motivation

• Test issues are addressed after final logic
  synthesis using gate-level SSF model
• Test generation and fault simulation using
  gate-level SSF suffers
• Prohibitively expensive run-time penalty
• Delayed architectural improvements to enhance DFT
  features
• Lack of an effective RTL fault model adversely
  affects cost, production quality and design cycle
  time

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Some Observations on RTL Faults

• RTL faults to have detection probability
  distribution similar to that of collapsed gate
  faults
• Statistically, an RTL fault-list resembles a
  random sample from the gate-level fault-list
• Number of RTL faults vs. gate faults depends on
• Level of RTL description
• Synthesis procedure used to convert RTL to gate
  level

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RTL Fault Model (ITC-2000)

• Language operators are assumed to be fault-free
• Variables (map onto signal lines) contain faults
• stuck-at-0
• stuck-at-1
• Only one fault is applied at a time (single fault
  assumption)

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RTL Fault Injection Algorithm

• Not affected by faults
• Synthetic operators ( - gt lt ! )
• Boolean operators ( )
• Logical operators ( ! )
• Sequential elements ( flip-flops latches )
• Faults introduced in signal variables Stems and
  fan-outs

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Coverage of RTL Faults

• Experimental results demonstrate RTL fault
  coverage of a module to be a good statistical
  estimate of the gate-level fault coverage
• Overall RTL fault coverage of a VLSI system with
  multiple modules does not represent the
  gate-level fault coverage

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Application of Stratified Sampling

• Fault population of a VLSI system divided into
  strata according to RTL module boundaries
• RTL faults in each module are considered a sample
  of corresponding gate faults
• The stratified RTL coverage of a VLSI system

M C S Wmcm m1
Wm stratum weight of mth module Gm/G cm RTL
fault coverage of mth module Gm number of gate
faults in mth module G number of all gate
faults in the system
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Application of Stratified Sampling

• Range of coverage,

C t s
Wm
M
s2 -------- cm(1 -
cm)
S
where,
rm - 1
m1
rm number of RTL faults in mth module t
value from tables of normal distribution

• The technique requires knowledge of stratum
  weights and not absolute values of Gm and G

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Stratum Weights

• Stratum weights derived from gate-level
  fault-list of the final netlist are accurate
• In RTL fault modeling, information about final
  netlist is not available
• Techniques proposed for early estimate of stratum
  weights (for RTL fault modeling) use
  observation-based assumptions

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Stratum Weights Assumptions

• Estimation of stratum weights from an early
  netlist
• Although absolute values of Gm and G obtained
  from different gate-level netlists (through
  constraint-driven logic synthesis runs) of the
  same RTL code vary significantly, their ratio
  presented as Wm does not vary as much
• Impact of difference between the estimated and
  actual stratum weights on the RTL coverage and
  error bounds is negligible
• Estimation of stratum weights from area
  distribution
• Distribution of gate faults of a VLSI system
  among its modules is proportional to their
  respective gate counts

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Stratum Weight Extraction Techniques

• Logic synthesis based weight extraction
• Wm Gm/G
• Floor-planning based weight extraction
• Wm Am/A
• Entropy-measure based weight extraction

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Experimental Procedure

• Technology-dependent weight extraction
• Several unique gate-level netlists obtained by
  logic synthesis from the same RTL code
• Each synthesis run performed using a different
  set of constraints, e.g., area optimization
  (netlist 1), speed optimization (netlist 2), or
  combined area and speed optimizations (netlists 3
  and 4)
• Strata weights calculated using gate-level fault
  lists of various synthesized netlists
• Technology-independent weight extraction
• Stratum weights calculated using area
  distribution among modules
• Each set of strata weights used to calculate RTL
  fault coverage and error bounds
• Impact of estimation error investigated

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Experimental Data Gate-fault and Area
Distributions
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Experimental Data Weight Distributions
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Experimental DataRTL Fault Coverage
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Experimental DataError Bounds
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Conclusion

• Main ideas of RTL fault modeling
• A small or high-level RTL module contributes few
  RTL faults, but large statistical tolerance gives
  a correct coverage estimate
• Stratified sampling accounts for varying module
  sizes and for different RTL levels that may be
  used
• Stratum weights appear to be insensitive to
  specific details of synthesis
• Advantages of the proposed RTL fault model
• High-level test generation and evaluation
• Early identification of hard-to-test RTL
  architectures
• Potential for significantly reducing run-time
  penalty of the gate-level fault simulation

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References

• P. A. Thaker, M. E. Zaghloul, and M. B. Amin,
  Study of Correlation of Testability Aspects of
  RTL Description and Resulting Structural
  Implementation, Proc. 12th Int. Conf. VLSI
  Design, Jan. 1999, pp. 256-259.
• P. A. Thaker, V. D. Agrawal, and M. E. Zaghloul,
  Validation Vector Grade (VVG) A New Coverage
  Metric for Validation and Test, Proc. 17th IEEE
  VLSI Test Symp., Apr. 1999, pp. 182-188.
• P. A. Thaker, Register-Transfer Level Fault
  Modeling and Evaluation Techniques, PhD Thesis,
  George Washington University, Washington, D.C.,
  May 2000.
• P. A. Thaker, V. D. Agrawal, and M. E. Zaghloul,
  Register-Transfer Level Fault Modeling and Test
  Evaluation Techniques for VLSI Circuits, Proc.
  Int. Test Conf., Oct. 2000, pp. 940-949.
• This presentation is available from
  http//cm.bell-labs.com/cm/cs/who/va

11/01/00
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High-Level Test