Level1 Central Track Trigger

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Level1 Central Track Trigger
Meenakshi Narain Boston University / Dzero
Collaboration Run2b trigger meeting, April 25th,
2002
Summary of work done in the Run2b L1CTT group
Results from Graham Wilson, Liang Han, Mike
Hildredth, input from Terry Wyatt, Marvin
Johnson, Fred Borcherding, U. Heintz

• Physics Justification
• Proposed Implementation
• Costs and Schedule

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Level1 Central Track Trigger

• Goals
• provide stand-alone track triggers
• combine tracking and preshower information to
  identify electron and photon candidates
• generating track lists that allow other trigger
  systems to perform track matching.
• A critical part of the L1 muon trigger (current
  design)
• Match tracks to L1 calorimeter candidates to
  identify electrons and taus (proposed upgrade)
• Used in Level2
• for identifying high pT electrons and muons
  candidates.
• The L2 Silicon Track Trigger (STT) uses these
  tracks for finding displaced tracks in the
  Silicon Microstrip Tracker which are from b-quark
  decays. The CTT therefore aims to provide tracks
  down to pT?1.5 GeV.

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Current Run2a Implementation

• Uses Central Fiber Tracker and preshowers
• Divide into 80 sectors (each 4.5o)
• Track Finding
• Define hits from using pairs of fiber in each
  axial layer (doublets)
• Compare doublet hits with predefined patterns to
  validate a track
• Use 4 independent pT bins (Thresholds 1.5, 3,
  5, 10)
• Find tracks in each bin

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Tracking Trigger

• Feed all axial fibers plus preshower into gate
  arrays
• Trigger if a fiber combination is consistent with
  PT gt (1.5,3,5,10) GeV
• Tag categories (incl. CPS info) track, isolated
  track, electron, ...

Trigger response for Z ee MC with 4 min.bias
overlayed
Red lines triggered tracks from Z
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Why Upgrade?

• Expected Run 2A performance
• 97 of muons with pT gt 50 GeV/c are
  reconstructed correctly
• Of the remaining 3, 1.9 of the tracks are not
  reconstructed at all
• 1.1 are reconstructed as two tracks due to
  detector noise
• Expected Run2B performance
• Significantly more challenging due to increased
  number of minimum bias interactions (4-5).
• Tracking trigger rate is expected to rise
  dramatically due to accidental hit combinations
  yielding fake tracks.
• The 5 GeV threshold track trigger is satisfied
  in more than 12 of beam crossings with 5 minbias
  interactions !

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Why Upgrade?

• Run2b trigger rates with the current design are
  strongly dependent upon the number of underlying
  minimum bias
• An increasingly compromised tracking trigger with
  luminosity!

Trigger rate for one track with pT gt 10 GeV
Probability for specific track trigger terms to
be satisfied in a given crossing
400KHz
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Paths for improvement

• A possible solution
• The fiber doublet is larger than the fiber
  diameter, which results in a widening of the
  effective width of a fiber to that of a doublet,
  decreasing the resolution of the hits that are
  used for track finding.
• Use individual fiber hits rather than doublets
• Inherently narrower and therefore has a reduced
  probability of selecting a random combination of
  hits

Fiber 1 Fiber 2 Fiber 3 Doublet
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
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Paths for improvement

• Use different schemes to get efficiency and
  rejections.
• Schemes
• all-singlet case (16 layers)
• mixed schemes
• some CFT layers are treated as pairs of singlet
  layers and the rest as doublets.
• Notation
• Upper case ? hits treated as doublets
• lower case ? singlet hits.
• ABCDEFGH 8 layers of doublets
• Run 2a CTT scheme
• abcdefgh 16 layers of singlets.

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Different Equation Schemes
Default Doublet Equations 16-Layer Singlet Equations 12-Layer Equations abcdEFGH 12-Layer Equations ABCDefgh 14-Layer Equations abcdefGH
Efficiency for pT gt10 96.9 99.3 98.6 97.3 99.2
Efficiency for 5lt pT lt10 91.1 97.8 92.8 90.8 91.6
Efficiency for fake pT gt10 5.8 0.4 1.6 1.4 0.7
Efficiency for fake 5lt pT lt10 8.0 0.7 2.4 2.4 1.6
Fake TTK(2,10) 0.7 0 0.13 0 0.03
Fake TTK(1,5) 12.1 1.1 3.7 3.7 2.2
Fake TTK(2,5) 2.2 0.05 0.4 0.08 0.13
Single muons overlaid on events containing
exactly six minimum bias interactions and put
through the detailed DØ simulation and the
modified trigger simulator.
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Diff Schemes of Equations
Singlet/Doublet Scheme Singlet/Doublet Scheme Relative of equations Average number of terms/equation
All doublets ABCDEFGH 1.0 8
All singlets abcdefgh 15.3 12.6
2 doublets 12 singlets abCdeFgh 10.5 11.4
2 doublets 12 singlets ABcdefgh 10.0 11.4
2 doublets 12 singlets abcdefGH 7.7 11.4
4 doublets 8 singlets ABCDefgh 5.7 10.3
4 doublets 8 singlets aBcDeFgH 5.6 10.2
4 doublets 8 singlets abcdEFGH 4.2 10.2

• Factor of 10 for 12singlets/2doublets
• Factor of 4-5 for 8singlets/4 doublets

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Effect of Inefficiencies

• Inefficiencies tend to cause explosion in number
  of equations.
• use npe8, threshold1.5
• For 16 singlet layer equations

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A viable scheme

• Use 16 singlet layer for high pT bin keeping high
  efficiency
• Use 12 singlets and 2 doublet layers for low pT
  bins and accept lower efficiency
• A factor of 10 more resources needed compared to
  Run2A

pT threshold (GeV) Efficiency Doublet /singlet scheme Resources relative to total Run 2A resources
pT gt 20 98 abcdefgh 28 x 1.5 x 0.075 3.15
pT gt 10 98 abcdefgh 28 x 1.5 x 0.075 3.15
pT gt 5 95 abcdefGH 6.2 x 1.4 x 0.2 1.3
pT gt 1.5 95 abcdEFGH 3.0 x 1.2 x 0.5 2.5
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Run2A L1CTT Implementation
System 7 crates, 3 separate chains axial
tracker central preshower DFEA - CTOC -
CTTT - MTM - L1FW (with L2 sidechain CTOC - CTQD
- L2CTT) Forward Preshower DFEF - FPSS - FPTT
- MTM -L1FW (with L2 side chain FPSS -
L2FPS) Central Preshower stereo
DFES-CPSS-L2CPS chain (Level 2 only)
Common Motherboard
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Digital Daughter board

• Digital Board daughter cards come in two flavors
• single width for Axial trigger (DFEA)
• double width for everything else
• DFEF, DFES,
• Collector ('octet') cards CTOC
• Concentrator ('singlet') cards CTTT.
• etc

DFE Daughtercard
Rebuild DFEA boards Replace FPGAs
Common Motherboard No changes needed
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Compare FPGA resources

• FPGA Logic Cells
• Run2a (Xilinx Virtex series)
• XCV400 10,800 (med, lo, hi)
• XCV600 15,552 (lowest pT)
• Run2b (Xilinx VirtexII series)
• XC2V6000 76,032 (2 low pT)
• XC2V8000 104,832 (2 hi pT)
• Can accommodate factor of 6 10 more resources
  compared to Run2a.

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FPGA Costs and Availability

• Proposed Run2B FPGA
• XC2V6000 - 2 low pT bins (900 each)
• XC2V8000 - 2 high pT bins (2000 each)
• Cost projections include 10 price reduction per
  quarter and procurement in Dec03.
• Footprint of these VirtexII series FPGA are
  different ? new Daughter cards (DFEA)
• Motherboards and all other daughter boards remain
  the same

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Cost
? 25 contingency
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Groups

• Simulation and Algorithm development
• Brown
• Kansas
• Manchester
• Notre Dame
• Hardware
• Boston University
• FNAL

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Schedule
Description of Task Completion Date
Prototype algorithm simulated using FPGA simulation tools 11/5/02
Target algorithm coded and simulated 6/11/03
Layout Prototype I boards 8/7/03
Develop test procedures 7/24/03
Assemble and test prototype I 12/2/03
Layout prototype II boards 11/21/03
Assemble and test prototype II 2/27/04
Test prototype II at FNAL with the full test chain 1/30/04
Design, Layout and Fabricate production boards 4/23/04
Daughter boards tested and ready for installation 11/3/04
Install and commission the trigger 6/1/05
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Fallback Options

• lowest pT bin prune eqns tighter, give up on
  extended pT, all of this coupled to performance
  of STT and needs to be studied.
• Keep very high eff only for 2 high pT bins only
• Alternative algorithm being considered (uses less
  equations a more dynamic/computational
  approach)

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Operations at 396ns

• Red 16 layer scheme and Green 8 layer scheme
• Rejection for 396 ns in Run2b (15 minbias events)
  with 16 layer scheme will be almost similar to
  8 layer with 5 minbias events