Joint DesignTime and PostSilicon Minimization of Parametric Yield Loss using Adjustable Robust Optim

1
Joint Design-Time and Post-Silicon Minimization
of Parametric Yield Loss using Adjustable Robust
Optimization

• Murari Mani, Ashish K Singh, and Michael
  Orshansky
• University of Texas at Austin

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Outline

• Post silicon tuning and motivation for joint
  co-optimization with design-time tuning
• Formal metrics of control and measurement
  complexity to parameterize design and
  optimization trade-offs
• Efficient co-optimization using adjustable robust
  optimization
• Effectiveness of co-optimization for different
  patterns of parameter variation and
  implementation overhead

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Parametric Yield Loss and Mitigation by
Post-silicon Tuning

• Process variability results in parametric yield
  loss
• Exponential dependence of leakage on process
  spread
• Inverse correlation between leakage and
  performance
• Tuning chips after manufacturing is an effective
  yield enhancing strategy
• Adaptive body biasing (ABB) tightens Fmax spread
• Improves power limited parametric yield

Source Intel
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Joint Design Time and Post Silicon Co-Optimization

• Design time optimization - Cost is fixed
  regardless of actual process conditions for each
  chip
• Lack ability to react to the actual conditions
  on the chip
• Both design-time optimization and post-silicon
  adaptivity fight against the same variability
  budget
• Optimal application of two techniques depends on
• Spatial structure of variability and inter- vs.
  intra-chip variability ratio
• Spatial granularity of adaptivity
• Effectiveness of body biasing for a given
  technology
• Co-ordination between design time and post
  silicon steps can produce a more optimal solution
• Derive a strategy to guide post-silicon tuning,
  and make the first-phase design decisions

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Contributions of this Work

• Formal framework for joint design time and post
  silicon co-optimization
• Two-stage optimization under uncertainty with
  recourse
• Design-time sizing and post-silicon tuning using
  adaptive body biasing
• Efficient solution using adjustable robust
  optimization
• Decision variables are affine policy of process
  parameters
• Introduce the notions of control complexity,
  measurement complexity and parameter complexity
• Help designers predict the amount of adaptivity
  needed

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Adjustable Robust Optimization Paradigm

• What is a formal way of describing our
  co-optimization?
• Optimization with recourse under uncertainty
• Traditional Two stage stochastic programming
  with recourse
• Exact solutions difficult for continuous random
  parameters
• Any non-linearity renders problem NP hard
• Unsuitable for CAD problems
• Adjustable robust optimization (robust
  optimization with recourse)
• Optimization under uncertainty but formulated for
  sets
• In some cases, can be used for chance-constrained
  (statistical) problems

First stage decisions ? Observation of uncertain
variables ? Tune decision variables
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Robust and Robust Adjustable Optimization

• Robust linear programming
• Adjustable optimization
• Some variables (second-stage) are allowed to
  depend on realizations of uncertain parameters
• Computationally tractable if adjustable variables
  are constrained to be affine functions of the
  uncertain variables
• Leads to affinely adjustable counterpart

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Choosing Affine Policy

• Joint Minimization of Parametric Yield Loss
• Design-time variable is size (w)
• Post-silicon optimization variable is body bias
  (DVSB)
• In our case adjustable variable is the amount of
  body bias DVSB
• Constrain DVSB to be affine function of uncertain
  process parameters
• p0, p1 and p2 are coefficients determined during
  optimization
• P (p0,p1,p2) is referred to as body bias policy

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Control and Parameter Complexities

• Effectiveness of tuning depends on spatial
  granularity of adaptability
• E.g. number of distinct body bias values allowed
• Control complexity n captures flexibility of
  adaptation
• But also area and routing overhead
• Amount of intra-chip variability influences
  effectiveness of tuning
• Difficult to compensate large intra-chip
  variability
• Parameter complexity

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Measurement Complexity

• Measurement infrastructure is an essential part
  of tuning methodology
• Measurement complexity, k
• Represents the amount of known information about
  the structure of variability
• Use a single measure k kl kv
• Effectiveness of tuning depends on measurement
  complexity
• Determines selection of optimal policy

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Incorporating Affine Policy into Objective

• Using first order delay and log-leakage models

• Leakage is log-normal. Expected value
• Using affine policy expression
• f0, f1, and f2 are linear functions of p0, p1
  and p2
• Notice we moved from problem of finding (w and
  DVSB) to finding (w and p)

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Formulating Separable Objective Function

• We separate dependence on w and p
• Let Io b w, where b is leakage per unit device
  width
• Let
• For a vector of gate widths w, expected block
  leakage
• Minimize expected leakage power under timing
  yield
• Objective function is linear in size w and
  exponential in p

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Problem Formulation and Solution Strategy

• Delay constraints are second order conic path
  delays
• where
• Final optimization problem
• For efficient solution, solve as a two phase
  optimization
• w phase sizing at fixed body bias
• Second Order Conic Program
• p phase find body bias at fixed size
• Non-linear, linearize around a fixed point
• Solution is a vector of sizes and optimal policy
  P(p0,p1,p2)

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Co-Optimization vs. Heuristic Post-Sizing Tuning

• Joint optimization should also be superior to
  disjoint tuning steps
• Performed comparison against heuristics that
  performs post silicon tuning separately after
  sizing
• Difficult to pick optimal value of body bias for
  cells in design
• Performs worse than joint optimization
• Delay spread is higher
• Leakage power consumption is greater

Co-Optimization
Heuristic Disjoint
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Delay Spread Reduction

• Joint optimization is successful in tightening
  the delay distribution

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Impact of Changing of Control Complexity

• Increasing number of individually adjustable
  circuit clusters allows significant reduction
  (for same parameter complexity)
• Achieved at the cost of increased implementation
  overhead
• Proposed optimization allows designers to explore
  trade-offs

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Impact of Parameter Complexity (Magnitude of
Intra-Chip Variability)

• As the amount of uncorrelated variability
  increases, benefit of post-silicon tuning is
  reduced
• More difficult to compensate individual regions
• Design time optimization performs better, though
  still inferior

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Impact of Increasing Measurement Complexity

• Increasing measurement complexity allows a larger
  reduction of leakage power
• Improvement depends on parameter complexity
• Larger intra-chip variation requires more sensor
  sites

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Conclusions

• Joint co-optimization enables synergy between
  design time and post silicon steps
• Developed foundation for joint design-time and
  post-silicon optimization
• Up to 20 savings in leakage power can be
  obtained
• Introduction of metrics that enable designers to
  assess the complexity of biasing circuitry needed
• Computationally efficient formulation using
  adjustable robust optimization
• Good run-time behavior