Specification and Design of QuasiDelayInsensitive Java Card Microprocessor

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Specification and Design of Quasi-Delay-Insensitiv
e Java Card Microprocessor

• Fu-Chiung Cheng Chuin-Ren Wang
• Dept. of Computer Science and Engineering
• Tatung University
• Taipei 104, Taiwan R.O.C.

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Outline

• 1. Motivation
• 2. Smart Card Architecture
• 3. Introduction of Java Card
• 4. Java Card Processor Organization
• 5. Specification Data Dependency Graph
• 6. Implementation and Optimizations
• 7. Conclusion

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1. Motivation

• ID card, driver license, credit cards, bank
  Cards, library card, pay-phone card, ...
• gt Smart Card
• Other applications Henry97
• fraud control for credit and debit cards
• access control for buildings or computer systems
  
• ticketless travel on airlines, subways, buses or
  trains.
• Java Card is a smart card using Java technology.

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1. Motivation

• Why Asynchronous circuit for Java Card
  Microprocessor? Hauck95,Cheng97
• low power consumption
• average-case performance
• robust
• Modularity, Composability, Reusability

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2. Smart Card Architecture

• Smart card architecture consists of
• CPU
• memory
• communication interface
• The front and back of Smart card

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2. Smart Card Architecture

• Smart Card CPU
• 8-bit, single-tasking devices with 1KB of RAM or
  less.
• On-Card Memory
• ROM (Read-Only Memory)
• RAM (Random Access Memory)
• EEPROM (Electrically Erasable Programmable Read
  Only Memory)

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2. Smart Card Architecture

• Communication Interface
• A smart card does not contain its own power
  supply, display, or keyboard.
• Card Acceptance Device (CAD)
• A smart card interacts with a Card Acceptance
  Device (CAD) through the communication interface

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3. Java Card

• Java Card is a smart card using Java technology.
• Java programs run on Java Virtual Machine (JVM).
• JVM is an interpreter to execute bytecodes (Java
  instructions).
• JVM is a stack-based machine.
• Java Card instruction set is a subset of Full
  Javas.

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3.1 Data type in Java Card

• Two kinds of types primitive types and reference
  types.
• Primitive types
• byte 8-bit signed twos-complement integer.
• short 16-bit signed twos-complement integers.
• int 32-bit signed twos-complement integers.
• Boolean 8-bit, TRUE or FALSE.
• Reference types
• class types, interface types, and array types.

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3.2 Java Card Instruction Set

• Java Card 2.0 has 104 instructions.
• 1. Load/ Store Instructions iload, istore, ....
• 2. Arithmetic Instructions iadd, isub, ior, ....
• 3. Type Conversion Instructions i2b, i2s.
• 4. Control Transfer Instructions ifnull,
  ifltcondgt
• 5. Operand Stack Management pop, dup, ....
• 6. Object Creation and Manipulation new,
  getfield
• 7. Method Invocation and Return Instructions
  invokespecial, invokestatic, return, .....
• 8. Throwing and Handling Exceptions athrow.

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4. JAVA Card Processor Organization
Control line
Bus line
PC program counter SP stack pointer IR
instruction register MAR memory address
register MI memory interface A, B
two general-purposed registers FB
Frame-based register
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5. Specification Data Dependency Graph

• Given an instruction set a processor
  organization, micro-operations of instructions
  may be specified by data dependency graphs
  Nanya94.
• The micro-operations can be directly mapped into
  quasi-delay-insensitive components.
• Five basic components fork, join,select, merge
  and oval (micro-operation).

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5.1 DDG Five Basic Elements
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5.2 DDG Java Card Processor
Fetch Instruction
Decode
Execution
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5.3 DDG iadd instruction
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6. Implementation

• Goal four-phase handshaking QDI circuits
  Nanya94,Cheng97.
• Mapping DDGs to QDI Components
• TITAC point-to-point data transfer
• Our Java Card Processor shared bus architecture.

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6.1 Shared Bus Architecture
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6.2 QDI Library
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6.3 Deriving Control Path from DDGs
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6.3 C-element and Q-element
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Control Path iadd
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6.3 Deriving Datapath from DDGs

• For each micro-operation, M, and its Q-element
  with the start (Ms) and finish (Mf) of this
  micro-operation
• If M read a register R then connect Ms to the
  read signal of R.
• If M write to a register R then connect Ms to the
  write signal of R and add a demultiplexer to send
  out the write acknowledge to Mf.
• If there are multiple signals connecting to a
  read/write signal, add an OR gate.

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Datapath
Control Path
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6.4 Optimization

• Goal better performance, less power consumption
  and/or less logic.
• Three optimization schemes
• Redundancy Elimination
• Parallel Execution
• Common Modularity

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6.4 Optimization Example 1
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6.4 Optimization Example 2

• Sharing Common modules

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6.4 Optimization Results

• Redundancy Elimination
• Micro-operations 12 ? 9
• Cost and power consumption save one addition and
  three data transmission operations.
• Parallel Execution
• Micro-operations 9 ? 8
• Common Modularity
• Cost save (n-1)getTwoOperands.
• (n is number of instructions in Arithmetic).

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7. Conclusions

• A new asynchronous Java Card microprocessor
  architecture is presented.
• Data dependent graph is used to specify the
  micro-operations of Java card microprocessor.
• Three optimization schemes are applied for better
  performance, less power consumption and/or logic.
  
• New Java Card 2.1 (Mar. 1999) spec contains 186
  instructions.
• We are developing CAD tool.