A LowPower LocalClocked Filter Bank Design for a Digital Hearing Aid

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A Low-Power Local-Clocked Filter Bank Design for
a Digital Hearing Aid

• B. Wongkittisuksa, N. Jindapetch, K.Tasanawipas
• W. Suntiamorntut, and P. Phukpattaranont
• Department of Electrical Engineering
• Faculty of Engineering, Prince of Songkla
  University
• Hat Yai, Songkhla, Thailand

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Contents

• Introduction
• Filter bank for hearing aid
• Target architecture
• Local clock generation
• Summary

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Introduction

• Why digital hearing aid ?
• Advanced DSP techniques
• more accurate sound reproduction
• minimum distortion and noise

A typical digital hearing aid
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Related work

• The custom ASIC approach
• Small size
• Ultra-low power
• The commercially available DSP chip
• Lower development cost
• Better sound quality
• However, the DSP chip must operate at high clock
  speed to obtain real time requirements.

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The propose approach

• Low power techniques on FPGA (Field Programmable
  Gate Array)
• Parallel processing
• High throughput for real time requirements
• Slower clock speed than DSP chip
• Local clock scheme
• Each module operates when activated
• No external crystal oscillator

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Filter bank for hearing aid
An 8-band filter bank based digital hearing aid
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An 8-band filter bank
Output signals from an 8-band filter bank
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Difference equations
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Our design target architecture

• Three parts a data-path part, a control part,
  and a local clock generation part.

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Data-path part
Inter-block Resource-sharing
Intra-block Resource-sharing
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Control part

• FSM (Finite State Machine)
• Generates multiplexer select signals
• Generates activate signals to pulse generation
  modules

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Local clock generation

• It is enabled by a request signal.
• No need the conventional clock circuitries (such
  as a clock delay locked loop and a digital
  frequency synthesizer).
• No need the external crystal oscillator.
• This scheme allows the proposed circuit can gain
  low-power operation and be implemented on a
  Xilinx FPGA.

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Summary

• A low-power 8-band filter bank design for a
  digital hearing aid on an FPGA (Field
  Programmable Gate Array) has been proposed.
• The proposed local clock scheme operating when
  requested achieved the low-power operation.