Principle of Hardware Design Design for testability Part A Chu Shik Jhon Seoul National University S

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Principle of Hardware DesignDesign for
testability (Part A)Chu Shik JhonSeoul
National UniversitySchool of Computer Science
and Engineering
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Testing

• Testing is one of the most expensive parts of
  hardware
• Logic verification accounts for gt 50 of design
  effort for many hardware
• Debug time after implementation has enormous
  opportunity cost
• Shipping defective parts can sink a company
• Example Intel FDIV bug
• Logic error not caught until gt 1M units shipped
• Recall cost 450M (!!!)

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DFT

• Design for testability (DFT)
• Design techniques that make test cost
  effective.
• Test cost
• Test pattern generation.
• Fault simulation cost.
• Fault location generation cost.
• Test equipment cost.
• Test process cost (time).
• Why DFT?
• Testing has become more difficult- NP complete
• Large number of gates per pin (see next slide)
• High cost of ATPG particularly for sequential
  circuits
• Need for a shorter design test cycle
• Shorter time-to-market

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Complexity Gates per Pin
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Controllability Observability

• Testability measures
• Controllability how easily the internal logic
  can be controlled from its primary inputs.
• Observability how easily the internal logic can
  be observed at its outputs

• Combinational logic is usually easy to observe
  and control
• Finite state machines can be very difficult,
  requiring many cycles
• to enter desired state
• Especially if state transition diagram is not
  known to the test engineer

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• Trade-off
• DFT requires extra circuits.
• - Increased H/W costs (Space).
• - Performance degradation (Time).
• DFT classification
• Ad Hoc design.
• - Not general (heuristic)
• - Test points, partitioning
• Structured design.
• - General (systematic, design rule)
• - LSSD, Full scan, Partial Scan, Built-in
  self-test (BIST), Boundary scan

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Ad Hoc DFT Methods

• Good design practices learnt through experience
  are used as guidelines
• - Avoid asynchronous (unclocked) feedback.
• - Make flip-flops initializable.
• - Avoid redundant gates.
• - Avoid large fanin gates.
• - Provide test control for difficult-to-control
  signals.
• - Avoid gated clocks.
• - Consider ATE requirements (tristates, etc.)
• Design reviews conducted by experts or design
  auditing tools.
• Disadvantages of ad-hoc DFT methods
• - Experts and tools not always available.
• - Test generation is often manual with no
  guarantee of high fault coverage.
• - Design iterations may be necessary.

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Ad Hoc DFT Methods
Test points For enhancing the controllability
and observability. Control Point (CP) primary
inputs to enhance controllability. Observation
Point (OP) primary outputs to enhance
observability.
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Major constraints I/O pins. Minimize of
additional I/O pins. Use MUX and DEMUX -
Increased test time (only one OP or CP)
time sharing I/O ports.
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• Good candidate for CPs.
• Control, address and data bus lines.
• Enable/hold inputs to microprocessors.
• Enable and read/write inputs to memory device.
• Clock and preset/clear inputs.

Initialization Design circuits to be easily
initialized
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Monostable multivibrators, oscillators and
clocks Disable internal one-shots, oscillators,
clocks during test
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• Partitioning large counters and shift registers
• Different to test (many clock cycles) - 16 bit
  counter 216 1 clocks
• 
  Two 8 bit counter 2 (28 1)
  clocks.

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• Partition large combinational circuits

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• Logical redundancy, global feedback paths
• Avoid the use of redundant logic.
• introduce faults which are not detectable using
  static test.
• Provide logic to break global feedback path.
• Using OPs, injection circuits (CPs).

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Scan Design

• Convert each flip-flop to a scan register
• Only costs one extra multiplexer
• Normal mode flip-flops behave as usual
• Scan mode flip-flops behave as shift register
• Contents of flops
• can be scanned
• out and new
• values scanned
• in

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Controllability/ observability via scan register
Scan registers Register with shift and parallel
load capacity
SSC
Q,S0
Q
D
Si
SSC
(a) A scan storage cell (SSC) (b) Symbol
for a SSC
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Scan in loading data into Scan Register from
Sin Scan out reading data out of Sout
D1
D2
Q1
Q2
Dn
Qn
D
Q
Q
Q
Si
Sin
Sout
...
SSC
SSC
N/T
CK
N/T
CK
(c)
N/T 0, normal mode, parallel data load (D) N/T
1, test mode data load from Sin
shifting
R
(d)
(c) A scan register (SR) or shift register
chain (d) Symbol for a scan register
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Variation using scan registers
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• Application example

Observe internal data via the OP lines thru
parallel load and scan out Control the CP lines
thru scan in operation
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Generic boundary scan Isolate one module from
the others using scan registers
If designed using boundary scan, tested by
scanning in test data into R2, and latching the
results into R1.
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• Generic scan design
• Employs a scan registers
• Several forms of scan designs
• differ primarily in how the scan cell designs
• Integrated scan registers
• scan registers that are part of functional
  registers
• Isolated scan registers
• not actually part of functional circuitry itself
• Advantage of scan path design
• Sequential circuit can be transformed into a
  combinational circuit
• Test generation is relatively easy
• Require very few extra I/O pins

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• Full integrated scan
• All original storage cells are made part of the
  scan registers
• The scan register is used as a serial shift
  register to achieve its scanning function

• N/T 0 normal mode
• Y easily controllable
• E easily observable
• Reduce
• test generation cost

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• Isolated serial scan
• Scan register is not in normal data part
• Scan/set design
• Selection of the CPs and Ops is left up to
  designer

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• Full isolated scan

1. Test vector is scanned into Rs 2. Loaded into
R and applied to C 3. Response is loaded
into Rs via R Pros) real time,
on-line testing
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Storage cells for scan designs Multiplexed data
F/F (MD-F/F)
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Two port dual clock F/F(2P-F/F) desirable to
insure race-free by non-overlapping
clock Multiplexed data shift register latch
(MD-SRL)
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• Two port shift register latch (2P-SRL)
• avoid the performance degradation by MUX in an
  MD-SRL
• use in level-sensitive scan design (LSSD)
• CK1 normal system clock
• CK2 scan data input clock
• CK3 L2 latch clock

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• Raceless dual port D F/F
• Used in scan path design
• Normal mode
• -gt SK 1 blocking scan data on Si (G1 1, D7
  1)
• -gt CK 0 enable data to be latched into master
• -gt CK 1 transferred to the slave
• Scan mode
• -gt CK 1 blocking data on D
• -gt SK 0 scan data on Si
• -gt SK 1 transferred to the slave