Ring Counter Based Delay Line

1
Ring Counter Based Delay Line

• In many wireless communication products, delay
  lines make up a significant portion of their
  circuits. Low power chips can be achieved by
  reducing the power consumption of delay line.
• A ring counter based delay line consists of a
  ring counter and a latch array.
• An address signal generated by the ring counter
  controls two adjacent latches. One is for
  write, and the other is for read.

2
Enable Signal Generation in the Ring Counter

• Not all of the registers need clock. Some
  registers are grouped in a block, and the clock
  signal is gated.
• C-elements are used to generate safe enable
  signals without input clock signals.

3
Gated-Clock-Driver Tree in the Ring Counter

• Gated clock architectures can be adopted again
  and again. A gated-clock-driver tree is
  developed.
• Loading capacitance M0xM1xM2xM3 ? M0M1M2M3
• If M0M1M2M and length is CxN, where NMk.
  The loading of clock becomes Cx Mx LogMN.
• D flip-flops can be replaced by double edge
  triggered flip-flops. and the clock rate is
  reduced.

4
Demultiplexer and Multiplexer in the Latch array

• The input bus in a latch array is replaced by a
  input driver tree--demultiplexer.
• The output bus is replaced by a output driver
  tree--multiplexer.
• The load decreases from LoadxN to LoadxMxLogMN.