Digital Integrated Circuits A Design Perspective

1
Digital Integrated CircuitsA Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje
Nikolic
The Devices
July 30, 2002
2
Goal of this chapter

• Present intuitive understanding of device
  operation
• Introduction of basic device equations
• Introduction of models for manual analysis
• Introduction of models for SPICE simulation
• Analysis of secondary and deep-sub-micron effects
• Future trends

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The Diode
Mostly occurring as parasitic element in Digital
ICs
4
Depletion Region
5
Diode Current
6
Forward Bias
Typically avoided in Digital ICs
7
Reverse Bias
The Dominant Operation Mode
8
Models for Manual Analysis
9
Junction Capacitance
10
Diffusion Capacitance
11
Secondary Effects
0.1
)
A
(
0

D
I
0.1
25.0
15.0
5.0
5.0
0
V
(V)
D
Avalanche Breakdown
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Diode Model
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SPICE Parameters
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What is a Transistor?
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The MOS Transistor
Polysilicon
Aluminum
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MOS Transistors -Types and Symbols
D
D
G
G
S
S
Depletion
NMOS
Enhancement
NMOS
D
D
G
G
B
S
S
NMOS with
PMOS
Enhancement
Bulk Contact
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Threshold Voltage Concept
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The Threshold Voltage
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The Body Effect
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Current-Voltage RelationsA good ol transistor
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Transistor in Linear
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Transistor in Saturation
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Current-Voltage RelationsLong-Channel Device
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A model for manual analysis
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Current-Voltage RelationsThe Deep-Submicron Era
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Velocity Saturation
Constant velocity
Constant mobility (slope µ)
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Perspective
I
D
Long-channel device
V
V
GS
DD
Short-channel device
V
V
V
- V
DSAT
DS
GS
T
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ID versus VGS
linear
quadratic
quadratic
Long Channel
Short Channel
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ID versus VDS
Long Channel
Short Channel
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A unified modelfor manual analysis
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Simple Model versus SPICE
(A)
D
I
V
(V)
DS
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A PMOS Transistor
VGS -1.0V
VGS -1.5V
VGS -2.0V
Assume all variables negative!
VGS -2.5V
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Transistor Model for Manual Analysis
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The Transistor as a Switch
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The Transistor as a Switch
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The Transistor as a Switch
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The Sub-Micron MOS Transistor

• Threshold Variations
• Subthreshold Conduction
• Parasitic Resistances

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Threshold Variations
Low
V

threshold
Long-channel threshold
DS
VDS
L
Threshold as a function of
Drain-induced barrier lowering
the length (for low
V
)
(for low
L
)
DS
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Sub-Threshold Conduction
The Slope Factor
S is DVGS for ID2/ID1 10
Typical values for S 60 .. 100 mV/decade
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Sub-Threshold ID vs VGS
VDS from 0 to 0.5V
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Sub-Threshold ID vs VDS
VGS from 0 to 0.3V
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Summary of MOSFET Operating Regions

• Strong Inversion VGS gt VT
• Linear (Resistive) VDS lt VDSAT
• Saturated (Constant Current) VDS ? VDSAT
• Weak Inversion (Sub-Threshold) VGS ? VT
• Exponential in VGS with linear VDS dependence

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Parasitic Resistances
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Latch-up
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Future Perspectives
25 nm FINFET MOS transistor