FEROM system

1
FEROM system

• The ALICE SSD sub-detector read out system
• FEROM Front End Read-Out Module
• Intro ALICE SSD sub-detector has 1698
  SSD-modules
• SSD-module
• SSD sub-detector overview
• FEROM SYSTEM
• Interfaces
• Partitioning
• FEROM Modules
• AD-module
• Link-module
• JTAG test control functions, radiation
  protection
• M.J. Rossewij, A.P. de Haas, J.A. Wisman,
• P.G. Kuijer, D. Killian

2
SSD module

• Double sided silicon strip detector, 768 strips
  per side.
• 12 HAL25 readout chips (121281536), Radhard,
  Lepsi
• HAL25 has 128 preamp, shapers and S/H, serial
  analog readout
• 5 Control signals HOLD, CLOCK, TOKEN, FastClear,
  TEST
• JTAG, 5 signals (set shaping time, bypass Token)

3
ALICE SSD sub-detector

• ALICE SSD sub-detector contains 1698 SSD-modules
• Layer 5 34 ladders, 22 SSD-mod. per ladder
• Layer 6 38 ladders, 25 SSD-mod. per ladder
• 2 ECM per ladder
• ECM connected with 10..13 SSD-mod.
• ECM mediates power and signals
• 10..13 analog signals
• 5 LVDS control signals
• 5 LVDS JTAG signals
• 1 LVDS error signal
• ECM developed at NIKHEF
• Per Side 72 ECMs, total 144 ECMs

4
FEROM system interface

• FEROM system communicates with
• 144 ECMs (1698 analog output signals)
• CTP (Central Trigger Processor)
• L0Busy via LVDS
• L1/L2 TTC system
• DAQ (DDL)
• DCS (JTAG)
• Slow Control (CAN)
• CTPgtTake 1536 samples from each ECM analog
  outputgtDAQ

5
FEROM system partitioning

• FEROM system accommodated in 2x4 crates
• Outside the magnet, 25 meter from ECMs
• Each crate has two 10 slot V430 backplanes
• Each backplane has 1 LINK module 9 AD modules
• FEROMV430 LINK-module 9 AD-modules
• BUFMUX buffers L0, multiplexes Busy
• 2 BUFMUX modules, one per side

6
FEROM interface

• Each AD-module interfaces with one ECM
• AD-module has 12 differential Analog inputs
• AD-module tasks
• Digitizing 12 analog input signals, Apply offset
  correction,
• Zero Suppression, Event Buffering
• Link-module interfaces with CTP, DAC, DCS
• Generating the 5 ECM control signals start
  digitalization signal
• (AD-module converts these control signals to LVDS
  (to ECM) )
• Read Out event data from AD-modules.

7
AD-module architecture

• ?200 AD-modules gt Effort to reduce cost price
• 12 inputs, functionality simple, low cost FPGAs
• 12 bit ADC digital offset correction, increase
  dynamic range
• MEB reduces dead time to 150 µs (SEB 400 µs _at_ 5
  occupancy)

8
AD-module MEB implementation gtSRAM

• FIFO gt not suitable due to L2-reject decisions
• Dual ported memory gt expensive (maybe netram)
• SRAM gt un-accessible for BusFPGA during ECM
  readout
• No problem due to dead-time low
  occupancy

9
FEROM BUS

• Standard VME64 too slow, and no 3,3V available
• Dedicated synchronous VME backplane protocol
  above cPCI
• Lower cost price
• More flexible, 3,3V 1,8V, Sending double words
• Easier to couple with the DDL, DDL-like protocol
• FEROM crate backplane split up in 2 x 10 slots
• Reducing scope single point failures
• Doubles data bandwidth due to doubling number of
  DDLs (30 MHz)
• Crates produced by Wiener, ordered via CERN ESS
  group
• Good supply and availability
• Using standard CAN control for crate power
  supplies and fans
• Slot number provides address Adm (data bus
  JTAG switch)
• AD-modules use standard combinatoric TTL
  comparators. (reduce SEU)

Backplane Type 2X10 Slot available Slot Numbering Extra IOs
VME64 Yes No No
VME64x No Yes Yes
gt VME430 YES YES YES
10
Link module

• Most link-module functionality implemented in 1
  FPGA
• DDL (SIU-piggyback)
• CTP (LVDS L0/BUSY, TTCrq piggy back)
• FEROM-bus
• Many signals (300 I/Os) gt FPGA in BGA package
• Advantages FPGA implementation
• FPGA introduces lot of flexibility.
• Link Module SEB implemented with FPGA DPM
• Xilinx VirtexII redundancy in input
  configuration.bits (reduce SEU)
• Link Module accommodates FPGA configuration
  PROMs.
• For AD-module and link-module FPGAs
• Radhard PROM optional
• Link module provides JTAG interface for DCS

11
JTAG SEU

• The ALICE SSD sub-detector uses JTAG for
• Control of the ECM HAL25 (shaping time/bypass
  token)
• Testing the interconnectivity
• Connectivity test of 5 control signals cabling
  until FEROM
• Using JTAG switches instead of large JTAG daisy
  chain
• Limits failure to the branch behind the switch
• JTAG switch uses VME430 Slot-number
• The AD-module ( link-module) JTAG-switch has 3
  ports
• ECM
• FPGA, readback and partial reconfiguration to
  correct SEU
• AD-module DCS functions (LED status, power supply
  status/control)

12
Conclusion

• FEROM system designed to readout the ALICE SSD
  sub-detector
• FEROM system features
• Large dynamic input range by using ADCs with 12
  bit resolution
• Low dead time by using MEB on AD-modules
• High data bandwidth bus with dedicated
  synchronous protocol
• High data bandwidth to DAQ by doubling DDLs (
  backplanes)
• (AD-module) cost price reduced by
• Using 12 analog AD-module inputs (rerouting ECM
  output 13)
• Using SRAM based MEB
• AD-module functionality simple, Low cost FPGA
• Share AD-module configuration PROM
• Low cost FEROM bus
• SEE effects (SEU latch up) reduced (low
  radiation dose)
• Using TTL address comparators with V430 Slot
  Numbers
• Parity over the measurement data, redundancy in
  virtex II configuration file
• AD-module link-module have poly switch fuses to
  protect against latch up.
• JTAG can be used for FPGA configuration readback
  and partial reconfiguration
• Scope single point failures reduced by
• Split-up of the backplane