ILP Models for the Synthesis of Asynchronous Control Circuits

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ILP Models for the Synthesis of Asynchronous
Control Circuits

• Josep Carmona and Jordi Cortadella
• Technical University of Catalunya
• Barcelona, Spain

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Outline

• Synthesis of Async. Circuits VME example
• State space explosion problem
• Structural methods
• Petri net methods. ILP for
• State encoding verification
• Decomposition of initial specification
• Design Flow
• Synthesis Example

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DSr
DSw
DTACK-
LDS
D
LDTACK
LDS
LDTACK-
D
LDTACK
DTACK
D-
LDS-
DSr-
DTACK
D-
DSw-
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DSr
DSw
DTACK-
LDS
D
LDTACK
LDS
LDTACK-
D
LDTACK
DTACK
D-
LDS-
DSr-
DTACK
D-
DSw-
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DSr
DSw
DTACK-
LDS
D
LDTACK
LDS
LDTACK-
D
LDTACK
DTACK
D-
LDS-
DSr-
DTACK
D-
DSw-
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DSr
DSw
DTACK-
LDS
D
LDTACK
LDS
LDTACK-
D
LDTACK
DTACK
D-
LDS-
DSr-
DTACK
D-
DSw-
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DSr
DSw
DTACK-
LDS
D
LDTACK
LDS
LDTACK-
D
LDTACK
DTACK
D-
LDS-
DSr-
DTACK
D-
DSw-
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Specification
?
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Signal Transition Graph (Petri net)
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00000
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The encoding problem
00000
01000
10000
DSr
DTACK-
LDS
LDTACK-
LDTACK-
LDTACK-
DSr
DTACK-
10010
LDS-
LDS-
LDS-
LDTACK
DSr
DTACK-
10110
01110
10110
D
D-
11111
10111
01111
DSr-
DTACK
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Boolean equations LDS D ? csc DTACK D D
LDTACK csc DSr
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State space explosion problem
Signal Transition Graph (Petri net)
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State space explosion problem

• Methods to avoid it
• Linear Algebra (LP/ILP)
• Graph Theory
• Implicit data structures (BDDs)
• Partiar order (Unfoldings)

Structural methods
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Marking equation
p1
Incidence matrix
p3
p2
p4
p5
p6
p7
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Marking equation
M M Ax
p1 p2 p3 p4 p5 p6 p7


Necessary reachability condition, but not
sufficient.
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Checking Unique State Coding
z a b a- b-
x
M0 M1 M2

• M1 and M2 have the same binary code (z must be
  a complementary set of transitions)
• M1 and M2 must be different markings (they
  must differ in at least one place)

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Checking Unique State Coding
z a b a- b-
x
M0 M1 M2
ILP formulation M1 M0 Ax M2 M1
Az bal(z) M1 ? M2 x, z, M1, M2 ? 0
bal(z) ? ?a (a) - (a-) 0
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Some experiments (USC)

• CLP (Khomenko et al)
• Partial order approach (Unfoldings)
• Integer Linear Programming

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Checking Complete State Coding
ILP formulation M1 M0 Ax M2 M1
Az bal(z) M1 ? ER(a) M2 ? ER(a) x, z, M1,
M2 ? 0
n ILP problems must be solved (n is the number of
transitions with label a)
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Some experiments (CSC)

• SAT (Khomenko et al )
• Partial order approach (Unfoldings)
• Satisfiability solver

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Synthesis

• Each signal can be implemented with asubset of
  the STG signals in the support(typically less
  than 10)
• Synthesis of a signal
• Project the STG onto the support signals (hide
  the rest)
• After projection, the STG still has CSC for the
  signal
• Use state-based methods on each projection

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Synthesis example
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Checking the support for a signal
Let ? be the set of signals and ? a potential
support for a. Let z be the projection of z onto
?. ? is a valid support for a if the following
model has no solution
ILP formulation M1 M0 Ax M2 M1
Az bal(z) M1 ? ER(a) M2 ? ER(a) x, z,
M1, M2 ? 0
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Algorithm to find the support
z a ? trigger signals of a forever z
ILP_check_support (STG, a, z) if z 0
then return z z z ? unbalanced signals
in z end_forever
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Experiments (Support Synthesis)
CPU
Literals
ILP
Petrify
Petrify
ILP

• Petrify (Cortadella et al )
• State-based technology mapping
• BDD

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Design flow
STG
structural encoding
remove internal signals and check CSC
STG with CSC
structural transformations
optimized STG
. . .
support for z
support for a
support for b
projection
STG for a
STG for b
STG for z
logic synthesis (petrify)
circuit for a
circuit for b
circuit for z
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Synthesis example
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x3
x1
x2
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z
x4
x5
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Conclusions

• Fast technique for state encoding checking,
  providing a speed-up of several orders of
  magnitude
• Novel technique for decomposing the spec
• Complete design flow for the synthesis of
  speed-independent circuits
• Can handle big-size specifications
• Quality comparable to state-based techniques

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Thank you!