ST7 Generalit

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Sistemi Elettronici Programmabili
ST7Generalità e core
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• THE ST7 VISION

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THE ST7 CORE

• Well-known Industry Standard 8-bit CISC
  architecture (Von Neuman)
• compatible with most popular cores
• 200 ns minimum instruction time with 1.375µs
  8x8 multiplication
• 64 KBytes linear addressing memory
• Indirect and Y index memory access
• Direct STACK management
• And many powerful added features ...

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STM A KEY PLAYER IN FLASH MEMORY
A VOLUME SUPPLIER Micros with embedded
non-volatile memory have been in high volume
production since 1998 Non-volatile memory
products 1 Billion units sold in 1998
MASTERING EMBEDDED FLASH SOLUTIONS Very high
reliability with 20 year retention Two solutions
for cost vs. feature optimization

• FLASH

eFLASH Data EEPROM capable
Flash
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• ST7 FLASH IN SITU PROGRAMMING
• WITH HIGH PROTECTION

• Patented high protection level on Flash, OTP and
  ROM versions

Piracy protection Unexpected writing protection

• In-situ programming for Flash and EEPROM

from any pins / peripheral interfaces (software
configurable)
Standalone mode (application running)
Remote mode (at production level)
Flexible production manufacturing
and test flow
On-the-fly application reprogramming
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• ST7 ANALOG PERIPHERALS
• MORE FLEXIBILITY LESS COMPONENTS

Low Voltage Detector
Op Amp
8- 10-bit ADC ... and more to come

• Up to 16 channels
• Fast conversion time 3 ms
• High resolution (5 mV)

Simple PCB No interrupt Less external components
Low power consumption Less external components
Embedded supply monitoring
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• LOW VOLTAGE DETECTOR CHARACTERISTICS

• LVD (IT) interrupt generation before
  entering reset
• LVD (reset) flag activation
• Selectable reset levels for
• 5 V applications 4.5 V - 5.5 V
• 3.3 V applications 3 V - 3.6 V
• ...

Context saving in EEPROM Origin of reset
localizable Saves external supply monitoring
circuitry
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• LOW VOLTAGE DETECTOR

• External components saved
• 2 Clamping diodes
• 4 Resistors
• 1 Transistor
• 1 Zener diode
• 1 Filter capacitor

• Integrated 3-level range on Low Voltage Detector
• Reset automatically activates when 0.8V lt VDD lt
  Safe Level
• External reset generation (30 µs)
• Internal interrupt reset generation

• Reset of other devices of the application
• Cost savings of 10 to 15 cents
• Enhanced reliability
• Safe micro behavior

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• INTEGRATED OPERATIONAL AMPLIFIER

• Rail-to-rail programmable op-amp
• Band gap
• Fixed voltage reference
• Programmable voltage reference
• 6.5 MHz bandwidth
• Auto-zero mode
• On/off capability
• Internal connection to ADC

• Can be used for
• ADC zooming
• Comparator / voltage threshold detector
• Peak voltage detector

ADC error suppression Low power consumption Cost
saving
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• ST7 LOW POWER SOLUTIONS

Oscillator
EMC by design
Low power modes
Low emission High robustness
lt 700 mA / 16 MHz
Low power and safe
Low power consumption
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• ST7 MULTI-OSCILLATOR SYSTEM

osc1
osc2

• Quartz / ceramic
• Up to 16 MHz

• Internal RC
• 1 MHz /- 1
• 4 MHz /- 20

• External source
• Up to 16 MHz

• External RC
• 1 to 14 MHz

• Low frequency backup safety oscillator
• Automatic switch from main clock to safe clock
• Dedicated flag Interrupt generation
• Watchdog always operational

• Internal safe oscillator
• 250 KHz /- 15

Power optimization Safe microcontroller behavior
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• ST7 LOW POWER MODES

Consumption 5V4MHz typical ST7 LOW POWER MODE FIT ALL YOUR APPLICATION REQUIREMENTS
1.8mA Core and peripherals run at max. frequency Selected peripheral can be switched off
600µA Core and peripherals run at Fosc2n
1mA Core frozen Peripherals run at max. frequency
350µA Core frozen Peripherals run at Fosc2n
300µA
0.2µA
RUN
SLOW
Real Time Clock
WAIT
SLOW-WAIT
ACTIVE-HALT
HALT

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• EMC APPROACH SECURE ROBUST

• Low power design
• Protected and robust macrocells
• Factual measurements through comprehensive
  testing
• Operation in noise sensitive environments can be
  evaluated from the information available in
  datasheet

• High protection
• Cost savings
• Fewer components on the board

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• ST7 PROGRAMMABLE I/Os
• PIN-BY-PIN FLEXIBLE CONFIGURATION

Output I/O port configuration example
Input I/O port configuration example

• High flexibility in I/Os and software
  configuration
• Fewer external components and less expensive PCB
  
• One microcontroller for different design versions
• Lower development and inventory cost
• Lower pin count and better pricing through
  economy of scale

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• ST7 A SET OF AVAILABLE PERIPHERALS

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ST7 TECHNICAL TRAINING
1 - INTRODUCTION 2 - CORE 3 - ADRESSING MODES 4
- PERIPHERALS 5 - ST7 SOFTWARE TOOLS 6 - ST7
HARDWARE TOOLS 7 - STVD7
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ST7 CORE
ST7 STACK
INTERNAL REGISTERS
LOW POWER MODES
INTERRUPTS
CLOCK CONTROLLER
RESET SYSTEM LVD
MEMORY SPACE
WATCHDOG
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ST7 CORE General Description

• THE ST7 CORE (Von Neuman Architecture) IS BUILT
  AROUND
• an 8-bit Arithmetic and Logic Unit (ALU)
• 6 internal registers Accumulator (A), X and Y
  index registers, Program Counter (PC), the Stack
  Pointer (SP) and the Code Condition register (CC)
• a controller block
• IT INTERFACES WITH
• an on-chip oscillator
• a reset block
• address and data buses to access memories and
  peripherals
• an interrupt controller

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ST7 COREBlock Diagram
OSCin
Mutli oscillator Clock controller
OSCout
Internal CLOCK
ISPSEL/ Vpp
CONTROL
8 -BIT ALU
Watchdog LVD Enhanced Reset
SP
Accu
PCL
Index X
DATA BUS
PCH
Index Y
CC
ADDRESS BUS
Program memory
RAM
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ST7 COREInternal Registers (1)

• The ACCUMULATOR is an 8-bit general purpose
  register used to hold
• Operands
• Results of arithmetic and logic operation
• The X and Y REGISTERS are two 8-bit registers
  used to
• Create effective addresses
• Store temporary data

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ST7 COREInternal Registers (2)

• The PROGRAM COUNTER PC is a 16-bit register used
  to store the address of the next instruction to
  be executed by the CPU. As a result, the ST7 can
  address up to 64k of program memory
• The STACK POINTER SP is a 16-bit register. The
  msb is fixed by hardware
• The CODE CONDITION CC is a 5-bit register

BIT NAME DESCRIPTION
H Half Carry Bit H1 when a carry occurs during ADD and ADC instructions
I Interrupt mask I1 disabled the interrupt
N Negative bit N1 if the result of the last operation is negative
Z Zero bit Z1 if the result of the last operation is zero
C Carry/Borrow bit Affected when carry or borrow out occur and some inst. are executed
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ST7 COREInternal Registers (3)
ACCUMULATOR
7
X INDEX REGISTER
0
Y INDEX REGISTER
PROGRAM COUNTER
STACK POINTER
CONDITION CODE REGISTER
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ST7 COREStack manipulation (1)

• PURPOSE
• Save the CPU context during subroutine calls or
  interrupts
• Save temporary user's data (PUSH and POP
  instructions)
• IN CASE OF OVERFLOW (LOWER LIMIT EXCEEDED)
• SP rolls over to the higher address
• Previous value is overwritten so lost
• Stack overflow is not indicated

• Pop Y
• Return from subroutines or interrupt

• Push Y
• Call subroutines or interrupt

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ST7 COREStack manipulation (2)
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ST7 COREThe memory space

• THE MEMORY CAN BE MADE OF 6 DIFFERENT BLOCKS
• Peripherals hardware registerI/O Ports, TIM,
  ADC, WDG,SPI, I2C, EEPROM etc
• Ram 0 ram in first page
• Stack from 128 to 256 bytes (device dependent)
• EEPROM Data (up to 256 bytes)
• Program memory
• Interrupt and Reset vectors

Short Addressing Mode Location
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ST7 IN-SITU PROGRAMINGRemote ISP

• What is it for ?
• To PROGRAM or REPROGRAM (flash devices) the
  Program Memory when the micro is soldered on the
  application board.
• Main features
• Only 6 wires are used (including VDD VSS).
• Do not need double voltage on the application
  board.
• Supported by the ST window eepromer tools.
• Performances
• 5 s to program 8Kbytes.

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ST7 IN-SITU PROGRAMING (ISP)Remote mode
I/Os
Boot-ROM
RAM
RAM

• 1

PROG MEMORY
Software executed in RAM programs the prog memory
PROG MEMORY
Boot-ROM allows an executable software to be
dowloaded in RAM through ISPCLK ISPDATA
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Memory CPU registerSummary

• How Many CPU registers belong to the ST7 Core?
• Is it possible to place and read data in ROM
  (program memory)?
• Is it possible to execute code located in RAM ?
• Is the Stack handle automatically by the ST7 core
  ?

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ST7 INTERRUPTSOverview

• EXCEPT FOR THE SOFTWARE INTERRUPT (TRAP
  Instruction), ALL INTERRUPTS CAN BE MASKED BY
  SETTING THE I BIT IN CC
• WHEN AN INTERRUPT OCCURS
• The context is saved on the stack (CC, A, X, PC)
• All other interrupts are masked (the I bit is set
  By H/W
• The interrupt vector is loaded in the Program
  Counter
• WHEN RETURN FROM INTERRUPT IS EXECUTED
• The original context is automatically restored
  (CC, A, X, PC)
• Interrupts are enabled (I bit reset)
• PRIORITY BETWEEN INTERRUPTS IS GIVEN BY THE
  INTERRUPT ADDRESS VECTOR

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ST7 INTERRUPTSST72254 Interrupt mapping
CPU INTERRUPT INTERRUPTS REGISTER FLAG NAME INTERRUPT SOURCE VECTOR ADDRESS
Reset Reset N/A N/A - FFFEh-FFFFh
Trap (instruction) Software N/A N/A I0 FFFCh-FFFDh
External Interrupt 0 Port A N/A N/A I1 FFFAh-FFFBh
External Interrupt 1 Port B and Port C N/A N/A I2 FFF8h-FFF9h
CSS Clock Filter Interrupt CRSR CCSD I3 FFF6h-FFF7h
SPI Transfer Complete Mode Fault SPI Status SPIF MODF I4 FFF4h-FFF5h
Timer A Input Capture 1 Output Compare 1 Input Capture 2 Output Compare 2 Timer Overflow Timer A Status ICF1 OCF1 ICF2 OCF2 TOF I5 FFF2h-FFF3h
Timer B Input Capture 1 Output Compare 1 Input Capture 2 Output Compare 2 Timer Overflow Timer B Status ICF1 OCF1 ICF2 OCF2 TOF I7 FFEEh-FFEFh
I2C Byte Transfer finished Bus Error STOP Detection I2C Status BTF BERR SSTOP I12 FFE4h-FFE5h
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ST7 INTERRUPTSPeripheral Int management
Periph Status Register
Interrupt flag set by H/W
X
X
X
X
1
X
X
X
Periph Control Register
Interrupt Enable bit set by S/W
X
1
X
X
X
X
X
X
Condition Code Register
Interrupt Mask bit set by S/W
H
N
C
1
1
1
0
Z

• Context switch takes 10 CPU clock cycles

Interrupt generation
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ST7 INTERRUPTPeripheral Int management

• SOFTWARE EXAMPLE.Main...BSET Control_reg,
  IT_enable Enable Periph interruptRIM
  Clear I bit in CC regis
• ... ie interrupt
  enabled.Int_routine...BRES Status_reg,
  IT_flag Avoid to process the
  
  same interrupt foreverIRET
  Return from interrupt...

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ST7 Interrupt Summary

• Interrupt Vectors
• Number
• S/W Priority
• Interrupt Reaction Time
• Automatic register pushed

• up 16 Vectors
• 16 levels hardwired
• 4 levels user configurable
• 1.250µs to 2.750 µs (end of the current
  instruction 10 cpu cycles)
• Program Counter, Accumulator, CC, X

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Concurrent Interrupt Management

• An interrupt can not be interrupted by another
  one
• Except by the NMI (Non Maskable Interrupt)

Software Priority
3
3
3
3
Hardware Priority
3
RIM
3
3/0
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Nested Interrupt

• The 4 interrupt S/W levels are set thanks to the
  pair of bits I0, I1.
• 1 pair of bits by interrupt vector stored in the
  ISPR registers
• The pair of bits is copied in the CC register
  when the corresponding IT is activated (software
  level greater than the current one).

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Nested Interrupt Management

• An interrupt can be interrupted by
• The NMI (Non Maskable Interrupt)
• An interrupt request having an highest software
  Priority

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Interrupt Roadmap
GP 42,44,56,64 pins
GP 28,32 pins
ST72104G1 ST72215G2 ST72216G1 ST72254G1/2
ST72314J2/4 ST72314N2/4 ST72334J2/4 ST72334N2/4
Concurent Interrupts
Concurent Interrupts
Auto 42,44,56,64 pins
Dedicated Solutions
ST72171K2 ST72411R1 ST72141K2
ST72532R4 ST72311R6/7/9 ST72512R4 ST72511R6/7/9
Nested Interrupts
Concurent Interrupts
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Interrupts Summary

• How many interrupt vectors can be used in the ST7
  ?
• Are the software interrupt levels able to be
  modified during the application?
• What are the instructions that enable disable
  the Interrupts?

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Multi oscillator (1)

• ADVANCED ST7 CLOCK SYSTEM
• Low frequency backup safety oscillator
• Implemented on Reprogrammable devices only

OSC1 OSC2
OSC1 OSC2
OSC1 OSC2
OSC1 OSC2

• EXTERNAL SOURCE

• EXTERNAL RC

• QUARTZ/CERAMIC

• INTERNAL 4Mhz

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Multi Oscillator (2)

• Frequency range
• 1 to 4 MHz
• 2 to 4 MHz
• 4 to 8 MHZ
• 8 to 16 MHz
• 1 to 14 MHz
• 4 MHz
• 250KHz

• 4 Crystal / Ceramic Oscillators
• Designed to reduce EMI consumption
  
• Low speed
• Mid low speed
• Mid high speed
• High speed
• 1 External RC Oscillator
• 1 Internal RC Oscillator
• 1 Internal Safe Oscillator

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Main Clock Controller
Clock Security System (CSS)
OSC1
fOSC
OSC2
Main Clock Controller (MCC)
CLKOUT
Clock Divider
MCCSR Register
fCPU
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Clock Security System

• Clock Filter Function
• Safe Oscillator ( 250KHz)

Main Oscillator Clock
Internal ST7 Clock
Main Oscillator Clock
Safe Oscillator Clock
Internal ST7 Clock
CSSD bit is set by H/W if one of the safety
function is activated and can generate a maskable
interrupt request
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ST7 CLOCK IN LOW POWER MODES

• RUN MODES FcpuFosc/2
• Core periph. running except if WAIT (Core
  stopped) selected
• SLOW MODES Division ratio from 4 to 32 by
  software
• Core periph. running except if WAIT (Core
  stopped) selected
• ACTIVE HALT Division ratio from 32000 to 400000
  by software
• Core periph. stopped but periodic wake-up
  through interrupts
• HALT MODE Oscillator stopped
• Core periph. stopped

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ST7 Clock System Roadmap
GP 42,44,56,64 pins
GP 28,32 pins
ST72104G1 ST72215G2 ST72216G1 ST72254G1/2
ST72314J2/4 ST72314N2/4 ST72334J2/4 ST72334N2/4
Multi oscillator RC ext. 4Mhz int. 20 Safety
oscillator SLOW 4/8/16/32 ACTIVE HALT
Multi oscillator RC ext. 4Mhz int. 20 Safety
oscillator SLOW 4/8/16/32
Auto 42,44,56,64 pins
Dedicated Solutions
ST72171K2 ST72411R1 ST72141K2
Idem as GP 28,32 pins
Quartz/Ceramic/Ext.clock4Mhz min SLOW4/8/16/32 A
CTIVE HALT
7.16Mhz int / Ext.Clock SLOW/32
ST72532R4 ST72311R6/7/9 ST72512R4 ST72511R6/7/9
Quartz/Ceramic/Ext.clock SLOW4/8/16/32
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ST7 COREReset diagram (1)

• EXTERNAL RESET USING RESET PIN
• Purpose allow to generate an external reset
• Condition reset pin pull low
• POWER SUPPLY DEPENDEND RESET USING LVD
• Purpose ensure the MCU is in a known state
  whatever Vcc
• Condition internal reset when Vcc reaches Vcc
  min
• WATCHDOG RESET USING THE WATCHDOG TIMER
• Purpose guarantee the safety in case of
  software trouble
• Condition internal reset when the WD register
  is not refreshed

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ST7 ENHANCED RESET SYSTEM

• 3 RESET SOURCES
• Watchdog
• Low Voltage Detection (LVD)
• External RESET pin

• COMPLETE RESET MANAGEMENT
• Flags on Reset sources
• Internal Reset externally issued to reset the
  whole application

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ST7 COREReset diagram (3)
VCC
Internal Reset
CK
Ron
COUNTER
TO ST7
NRESET (ACTIVE LOW)
RESET
LVD RESET
WATCHDOG RESET
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NEW ST7 LVD GENERATION
Safe behaviour despite starting current sunk
VCC supply
VLVDr
250mV hysteresis
VLVDf
Min working VDD
RESET
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3 LVD LEVELS TO OPTIMIZE THE SAFE AREA
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LVD PART OF COMPLETE RESET MANAGEMENT
Software clearance
LVDRF
WDGRF
Vdd supply
LVD Reset ensures a stable cleared state of the
WDGRF when CPU starts

External
LVD
LVD
WDG
WDG
LVD
Original RESET source LVDRF WDGRF
External RESET pin 0 0
Watchdog Reset Flag 0 1
Low Voltage Reset Flag 1 X
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ST7 WATCHDOGOverview (1)

• ITS PURPOSE IS TO DETECT THE OCCURENCE OF A
  SOFTWARE FAULT. IT MUST BE REGULARLY REFRESHED BY
  THE PROGRAM
• ld WDCR, FF Reload WD
• 2 DIFFERENT WATCHDOG CAN BE SELECTED BY OPTION
  MASK
• Hardware Watchdog WD automatically activated
  upon reset
• Software watchdog it is activated by software
  (bit 7 1). Once activated, it cannot be
  disabled

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ST7 WATCHDOGOverview (2)

• RESET AND WATCHDOG
• HALT instruction can generate a reset if watchdog
  activated and if the option byte allows it
• The Watchdog can be used to generate a software
  reset (bit 7 1, bit 6 0)ld WDCR, 80
  Reset !

• Min WDCR C0hD 20 12288 12288 clock
  cycles 1.54 ms for Fcpu 8MHz
• Max WDCR FFhD 26 12288 786432 clock
  cycles 98.30 ms for Fcpu 8MHz

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ST7 WATCHDOGBlock diagram
Watchdog Status Register
Reset
Activation bit (WD active if set)
WDGF
-
-
-
-
-
-
-
Watchdog Control Register
WDGA
MSB
LSB
7-bit Down Counter
Fcpu
Clock Divider 12288
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LVD ROADMAP
GP 42,44,56,64 pins
GP 28,32 pins
ST72104G1 ST72215G2 ST72216G1 ST72254G1/2
ST72314J2/4 ST72314N2/4 ST72334J2/4 ST72334N2/4
3 LVD levels 4.00V/4.25V 3.60V/3.85V 3.10V/3.35V
Reset Flags
3 LVD levels 4.00V/4.25V 3.60V/3.85V 3.10V/3.35V
Reset Flags
Auto 42,44,56,64 pins
Dedicated Solutions
ST72171K2 ST72411R1 ST72141K2
Idem as GP 28,32 pins
LVD by device reference 4.25V/4.50V
1 level LVD
ST72532R4 ST72311R6/7/9 ST72512R4 ST72511R6/7/9
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Clock Reset systemSummary

• What are the maximun oscillator frequency and the
  maximun CPU frequency ?
• How many internal RC oscillator are implemented
  on the ST7 ?
• What are the internal reset sources?
• Are these internal resets can detected
  externally?

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ST7 LOW CONSUMPTION MODESOverview

• MAXIMUM CONSUMPTION 20 mA WITH FOSC 16 MHZ
  AND VDD 5V
• TO REACH LOWEST POWER CONSUMPTION
• Switch off unused peripherals
• Configure I/Os as output low level and connect
  them to GND
• Use the lowest oscillator frequency possible
• Use the Slow mode, Wait mode or better the Halt
  mode
• DATA RETENTION VOLTAGE IN HALT MODE 2V

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ST7 LOW CONSUMPTION MODESSlow mode

• GOAL reduce the comsumption by reducing the
  clock speed keeping the same Oscillator
  frequency
• ENTER BY configuring the miscellaneous
  register
• CAUSES the CPU clock slows down
• the Fosc can be divided by 4, 8 ,16 or 32 rather
  than 2
• EXIT BY configuring the miscellaneous register

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ST7 LOW CONSUMPTION MODESWait mode

• GOAL Reduce the consumption while monitoring
  external events
• ENTER BY execution of the WFI instruction
• CAUSES the micro is software frozen
• Program execution stopped
• Memory and registers remain unchanged
• The oscillator still provides a clock to the
  peripherals
• EXIT BY
• Reset (Watchdog, reset pin)
• Internal interrupts (timer A, timer B, A/D, SPI
  etc)
• External interrupts (I/O ports)

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ST7 LOW CONSUMPTION MODESActive Halt mode

• GOAL Reduce the consumption to the lowest value
  while monitoring a real time clock.
• ENTER BY execution of the HALT instruction
  while the OIE (Oscillator Interrupt Enable) bit
  is set.
• CAUSES the micro is SW frozen, all the
  peripherals are stopped, only the Oscillator
  the Main Oscillator Counter are running.
• EXIT BY
• External Reset
• Interrupts with exit from halt capability
  (External IT,..)
• Time Base Interrupt (32000,64000,160000,400000
  Tcpu
• From 2ms to 25ms with fOSC16MHZ

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ST7 LOW CONSUMPTION MODESHalt mode

• GOAL Reduce the consumption to the lowest
  value
• ENTER BY execution of the HALT instruction
• CAUSES the micro is SW and HW frozen
• Program execution stopped
• Memory and registers remain unchanged
• The oscillator stopped
• EXIT BY
• External Reset
• External interrupts (I/O ports)

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PROGRAMMING TIPSLow Consumption Modes (1)

• DURING WAIT MODE or HALT MODE, BIT I (INTERRUPT
  BIT) OF CC REGISTER IS AUTOMATICALLY RESET TO
  ENABLE INTERRUPT
• TYPICAL CONSUMPTION

ST72254 ST72334
Run mode (Vdd5V, Fcpu8MHz) 5.5 mA 7.1 mA
Slow mode (Vdd5V, Fcpu500KHz) 0.7 mA 1 mA
Wait mode (Vdd5V, Fcpu8MHz) 2 mA
Wait minimun mode (Vdd5V,Fcpu500KHz) 0.4 mA 0.5 mA
Active Halt mode (Vdd5V,Fosc16MHz) - 20µA
Halt mode (Vdd5V) 0.5 µA 0.5 µA
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PROGRAMMING TIPSLow Consumption Modes (2)

• AFTER EXITING FROM HALT MODE OR WAIT MODE AFTER
  RESET, THE MICRO WAITS 4096 CPU CLOCK CYCLE
  (STABILIZATION TIME) BEFORE BEING OPERATIONAL
• SOURCE THAT ALLOWS TO EXIT FROM WFI OR HALT MODE
• Internal Interrupts gt Wait and Halt modes
• External Interrupts gt Halt mode