Ketan%20Patel,%20Igor%20Markov,%20John%20Hayes%20{knpatel,%20imarkov,%20jhayes}@eecs.umich.edu%20University%20of%20Michigan

1
Ketan Patel, Igor Markov, John Hayesknpatel,
imarkov, jhayes_at_eecs.umich.eduUniversity of
Michigan
Evaluating Circuit Reliability Under
Probabilistic Gate-Level Fault Models

• Abstract
• Circuit reliability is an increasingly important
  design consideration for modern logic circuits.
  To this end, our work focuses on the evaluation
  of circuit reliability under probabilistic
  gate-level fault models that can capture both
  soft errors, e.g., radiation-related, and
  spatially-uniform manufacturing defects. This
  basic task can, in principle, be used
• by synthesis procedures to select more reliable
  circuits
• to estimate yield for electronic nanotechnologies
  where high defect density is expected.
• We propose a matrix-based formalism to compute
  the error probability of the whole circuit based
  on probabilities of specific gate errors. This
  formalism is surprisingly related to that of
  quantum circuits, but also exhibits several new
  features. The numerical computation of error
  probabilities in large circuits runs into the
  same scalability problems as the simulation of
  quantum circuits. Therefore, we hope to adapt
  recent advances in quantum circuit simulation to
  the context of this work.

Probabilistic Transfer Matrix Probabilistic
transfer matrix row indices represent
outputs values column indices represent
inputs values Matrix elements capture pairwise
transition probabilities Example
Probabilistic AND gate

• Motivation
• Current fault models dont address transient
  failures
• Need probabilistic fault models
• Circuit reliability depends not only on
  faultiness of gates
• but also on circuit structure
• Need method to incorporate circuit structure
• Probabilistic Fault Model
• Assume gates gives an incorrect output with some
  probability.
• Example
• Probabilistic AND gate

00 01 10 11
inputs
0 1
probability output is 1 when input is 10
output
Component Interconnections
The circuit reliability can be determined from
its probabilistic transfer matrix The
probabilistic transfer matrix for a circuit can
be determined from those of its gates, using
operations corresponding to three basic methods
of composition serial, parallel and fanout
connections.
Serial Connection
A
B
B is the prob. transfer matrix of component B
with columns corresponding to invalid inputs
removed.
BA
Circuit Example Consider two circuits
implementing the function bac

• Fault-tolerant Circuits
• Fault-tolerant circuits can be analyzed using our
  formalism.
• encoded inputs
• ? columns in probabilistic transfer matrix
  corresponding to non-codewords eliminated
• encoded outputs
• ? ideal transfer matrix modified to have
  multiple ones in each column, corresponding
  to each of the possible correct outputs

a b c
INV OR (AND ? AND)
OR (AND ? INV) (INV ? INV ? I2)

• Ongoing Work
• Incorporate into circuit synthesis methods
• BDD-based methods to counter scalability issues
• ? similar methods have been used for quantum
  simulation
• Software for automated circuit reliability
  analysis
• Connections to quantum computing
• Other formalism for evaluating circuit
  reliability
• Reliability analysis for special circuits
  structures

Relation to Quantum Simulation
Similarities
Differences
Quantum simulation Our formalism
No fanout Fanout
Square matrices Rectangular matrices
Complex, unitary matrices Real matrices
Final step measurement Final step error probability calculation
Quantum simulation Our formalism
Gate operations Represented by matrices Represented by matrices
Serial connections Represented by matrix product Represented by matrix product
Parallel connections Represented by tensor product Represented by tensor product
Matrix size Doubly exponential Doubly exponential