CS 641: Computer Architecture

1
CS 641 Computer Architecture

• Professor Norm Rubin
• email norm_at_cs.umb.edu

2
Course Objectives

• Provide comprehensive introduction to computer
  architecture and organization
• Gain some insight into nature of design process
  and the associated trade-offs
• Help bridge some of the software, hardware, and
  firmware gaps

3
Grading

• Homework 10
• Reading quiz 5
• Projects 15
• Midterm1 (Virtual memory) 20
• Midterm2 (Assembly language) 20
• Final (Everything) 30

4
What are Machine Structures?
Application (Netscape)
Operating
Compiler
System (Windows 98)
Software
Assembler
Instruction Set Architecture
Hardware
I/O system
Processor
Memory
Datapath Control
Digital Design
Circuit Design
transistors

• Coordination of many levels of abstraction

5
What is a computer?

• Components
• input (mouse, keyboard)
• output (display, printer)
• memory (disk drives, DRAM, SRAM, CD)
• network
• Our primary focus the processor (datapath and
  control)
• implemented using millions of transistors
• Impossible to understand by looking at each
  transistor

6
Levels of Representation
temp vk vk vk1 vk1 temp
High Level Language Program (e.g., C)
Compiler

• lw to, 0(2)
• lw t1, 4(2)
• sw t1, 0(2)
• sw t0, 4(2)

Assembly Language Program (e.g.,MIPS)
Assembler
Machine Language Program (MIPS)
0000 1001 1100 0110 1010 1111 0101 1000 1010 1111
0101 1000 0000 1001 1100 0110 1100 0110 1010
1111 0101 1000 0000 1001 0101 1000 0000 1001
1100 0110 1010 1111
Machine Interpretation
Control Signal Specification

7
Anatomy 5 components of any Computer
Personal Computer
Keyboard, Mouse
Computer
Processor (active)
Memory (passive) (where programs, data live
when running)
Devices
Disk (where programs, data live when not
running)
Input
Control (brain)
Datapath (brawn)
Output
Display, Printer
8
Overview of Physical Implementations
out of which we make systems.

• Integrated Circuits (ICs)
• Combinational logic circuits, memory elements,
  analog interfaces.
• Printed Circuits (PC) boards
• substrate for ICs and interconnection,
  distribution of CLK, Vdd, and GND signals, heat
  dissipation.
• Power Supplies
• Converts line AC voltage to regulated DC low
  voltage levels.
• Chassis (rack, card case, ...)
• holds boards, power supply, provides physical
  interface to user or other systems.
• Connectors and Cables.

9
Technology Trends Memory Capacity(Single-Chip
DRAM)
year size (Mbit) 1980 0.0625 1983 0.25 1986
1 1989 4 1992 16 1996 64 1998 128 2000 256 2002 5
12

• Now 1.4X/yr, or 2X every 2 years.
• 8000X since 1980!

10
Technology Trends Microprocessor Complexity
Itanium 2 410 Million
Athlon (K7) 22 Million
Alpha 21264 15 million Pentium Pro 5.5
million PowerPC 620 6.9 million Alpha 21164 9.3
million Sparc Ultra 5.2 million
Moores Law
2X transistors/Chip Every 1.5 years Called
Moores Law
11
Technology Trends Processor Performance
Intel P4 2000 MHz (Fall 2001)
1.54X/yr
12
Computer Technology - Dramatic Change!

• State-of-the-art PC when you graduate (at least)
• Processor clock speed 5000 MegaHertz (5.0
  GigaHertz)
• Memory capacity 4000 MegaBytes (4.0 GigaBytes)
• Disk capacity 2000 GigaBytes (2.0 TeraBytes)
• New units! Mega gt Giga, Giga gt Tera

13
Computer Technology gt Dramatic Change

• Processor
• 2X in speed every 1.5 years 100X performance in
  last decade
• Memory
• DRAM capacity 2x / 2 years 64X size in last
  decade
• Cost per bit improves about 25 per year
• Disk
• capacity gt 2X in size every 1.0 years
• Cost per bit improves about 100 per year
• 120X size in last decade

14
CS641 So what's in it for me?

• Machine structures from a programmer's view
• What the programmer writes
• How it is converted to something the computer
  understands
• How the computer interprets the program
• What makes programs go slow

15
Chips

• Setting The Scene
• The Production of Semiconductors
• The Economics of Making Semiconductors

16
Integrated Circuits (2003 state-of-the-art)

• Primarily Crystalline Silicon
• 1mm - 25mm on a side
• 2003 - feature size 0.13um 0.13 x 10-6 m
• 100 - 400M transistors
• (25 - 100M logic gates")
• 3 - 10 conductive layers
• CMOS (complementary metal oxide semiconductor)
  - most common.

Bare Die
Chip in Package

• Package provides
• spreading of chip-level signal paths to
  board-level
• heat dissipation.
• Ceramic or plastic with gold wires.

17
Printed Circuit Boards

• fiberglass or ceramic
• 1-20 conductive layers
• 1-20in on a side
• IC packages are soldered down.

18
Equipment and materials at the start of the food
chain
Other Electronic Components
End Applications

• Passives (resistors, capacitors)
• Displays (CRTs, LCDs)
• Storage (disc drives)

Communications

• Enabling
• Manufacturing Process
• Design
• Modelling/Simulation
• Test Equipment

Software
Industrial
Semiconductor Materials

• Operating system
• Application software

• Silicon
• Compounds
• Gas Purification
• Ceramics

Data Processing
Semiconductors

• Integrated Circuits
• Microprocessors
• Memories
• Custom Logic
• Multiplier
• Discretes
• Photonics

Electronic Packaging
Consumer Electronics
Semiconductor Manufacturing Equipment

• Wafer Scale Integration
• 3-D Silicon
• Multichip Modules
• Discretes
• Hybrids
• Printed Wiring Boards
• Coatings
• Printed Circuit Boards
• Materials

• Plasma Etching
• Lithography
• Ion Implantation
• Diffusion Furnaces
• Chemical Vapour Depostion

Automotive
Source Deutsche Bank
19
Semiconductors Are Small

• The proliferation of semiconductors is due to
  their incessant miniaturisation (0.18 micron
  1/500 width of human hair)
• 64 million transistors fit into 21cm2
• 15 dimension reduction per annum
• Moores Law semiconductor costs half every 12-18
  months - driven by lithography

Human Hair
100
Microns
Pollens
White Blood Cells
10
Smog
Red Blood Cells
Bacteria
0.18 micron
1.0
Smoke
Virus
0.1
Source IBM Microelectronics
20
Making Silicon Wafers

• A seed crystal of ultra-pure silicon is suspended
  in a bath of molten silicon
• The crystal is slowly pulled up and grows into a
  cylindrical ingot of pure silicon
• The ingot is ground down to a uniform diameter
  cylinder (200mm/300mm ...)
• The end is cut off, then thin silicon wafers are
  sawn off (sliced) and polished
• The polished wafers are shipped to the
  semiconductor manufacturer to begin the front-end
  process
• Silicon wafers are ultra flat
• analogy if 300mm wafer corresponds to the
  earths equator, flatness 10 metres

Source Deutsche Bank
21
The Front-End Process
Bare Wafer

• Output is an array of semiconductor die
  (individual semiconductor devices) on a
  semiconductor wafer
• A batch process each wafer contains multiple
  (1-10M) die
• A repetitive process but with different materials
  (conductor, insulator, semiconductor) patterns
  (the design)
• Cleaning, inspection and diagnostics occur after
  almost every process step

i) Film Deposition
Wafer with Deposited Layer
The Patterning Process
ii) Lithography/Masking
Wafer with Temporary Resist Pattern
20-30x
Cleaning, Inspection, Diagnostics Automation
iii) Etch
Wafer with Permanently Patterned Layer
iv) Implant/Diffusion
Wafer with Altered Electrical Properties
Finished Wafer
Source Deutsche Bank
22
The Principal Of Front-End ProcessingPatterning
stacked layers

• A semiconductor device consists of patterned and
  stacked electronic materials - 20-30 layers
• semiconductor active transistor
• conductor electrical interconnection of
  independent transistors
• insulator electrical isolation of different
  interconnections dielectric
• Each patterning step corresponds to a different
  mask

Conductor
Insulator
Active transistor
The Different Stacked Layers
The Different Patterning Steps
Source Deutsche Bank, In-Circuit Engineering
23
The Patterning ProcessLithography Etch
Film
Wafer

• Lithography provides a temporary pattern (stepper
  / scanner)
• Etch makes the temporary pattern permanent

Lithography
1. Photoresist Application Spin coat a thin layer
of photoresist on surface
Mask
2. Alignment and Exposure Precise alignment of
mask/reticle to wafer and exposure of photoresist
3. Development Removal of unpolymerised resist
Etch
4. Etch Top layer of wafer is removed through
opening in resist layer
5. Photoresist Removal Remove remaining
photoresist layer from water
Source Deutsche Bank
24
The Lithography Process An extremely high
resolution printing process

• Several process steps
• photoresist application apply photosensitive
  material
• layer alignment pattern exposure
• align current layer to previous layer (accurate,
  high-speed)
• expose wafer surface to light through a patterned
  mask (reticle) - changes chemical properties of
  exposed photoresist
• development removed exposed photoresist areas
  through immersing entire wafer in solvent
• Lithography driven by
• smaller wavelengths of exposing light
• higher numerical aperture lenses - concentrate
  light waves
• other factors - tricks! (optical proximity
  correction - OPC phase-shift masks - PSM ...)

25
The Etch Process

• Removes unwanted material from top surface of
  wafer (normally in areas where photoresist has
  been removed)
• Creates a permanent pattern in surface layer
  material (in insulator, conductor, semiconductor)
• Process can be
• dry gas/plasma, higher precision, expensive
• wet liquid (acid), low precision, inexpensive
• Dry etch is most common and involves charged gas
  plasma bombarding wafer surface - mix of physical
  chemical reaction

26
Improving Economics Smaller Die Size (Die
Shrink)

• Employ lithography to create smaller feature
  sizes
• Die size to linewidth relationship is a
  square-function
• This is Moores Law in practice - 15 per annum
• On-track till at least 2007/8 (optical
  lithography)

0.5x
0.5 micron Resolution 100 Die Per Wafer
0.25 micron Resolution 400 Die Per Wafer
4x
Source Deutsche Bank
27
Improving Economics Wafer Size Increase

• Larger wafers provide lower unit costs
• Transition from 200mm to 300mm has (theoretical)
  2.25x area increase
• Investments increase 1.5x
• Upgrade to larger wafer size equipment only
  feasible when whole infrastructure (equipment,
  wafers, automation) is sufficiently mature
• Wafer size transitions have historically taken
  8-9 years

100mm
125mm
150mm
200mm
Relative Die Cost
300mm
Wafer Diameter (mm)
Source Deutsche Bank, In-Circuit Engineering
28
Improving Economics Yield

• Yield relates to the number of good die on each
  wafer - can vary from 30-95
• Yield can be impacted by
• contamination
• defective processing
• Retaining high yields requires cleanroom
  environment and process control (materials,
  parameters ...)
• For same process/product, yields generally
  improve over time - experience curve

High Contamination
Low Contamination
Low Yield
High Yield
Source Deutsche Bank
29
Moores Law Drives The Semiconductor Industry

• The number of transistors on a chip doubles every
  18-24 months
• . requiring 15 linewidth reduction every year

10G
4 Gb
1 Gb
1G
256 Mb
Memory (DRAM)
Pentium IV
64 Mb
100M
16 Mb
PIII
10M
4 Mb
PII
1 Mb
Pentium
1M
Transistors / chip
256 Kb
80386
80486,680
64 Kb
68020
100K
16 Kb
80286
4 Kb
Microprocessor
68000
8086
10K
8085
8080
4004
1K
1970
1975
1980
1985
1990
1995
2000
2005
Source In-Circuit Engineering