Built-In%20Test%20and%20Calibration%20of%20DAC/ADC%20Using%20A%20Low-Resolution%20Dithering%20DAC

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Built-In Test and Calibration of DAC/ADC Using A
Low-Resolution Dithering DAC

• Wei Jiang and Vishwani D. Agrawal
• Electrical and Computer Engineering
• Auburn University
• 17th IEEE North Atlantic Test Workshop

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Outline

• Overview
• Test of DAC
• Polynomial fitting algorithm
• DAC calibration by dithering DAC
• Test and calibration of ADC
• Simulation results
• Summary

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Overview

• Built-in test solution for mixed-signal
  system-on-chips (SoCs)
• Testing and characterizing non-linearity of
  on-chip DAC/ADCs
• Output calibration and error compensation for
  better linearity
• Low cost for design and manufacturing

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Typical Mixed-signal SoC
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Non-linearity Errors
INL error
INL error
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Proposed BIST Scheme
Lineardigital code outputs
Linearanalog outputs
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Third-Order Polynomial Fitting

• Proposed by S.K. Sunter in ITC96
• Divide DAC transfer function into four sections
• Combine function outputs of each section (S0, S1,
  S2, S3)
• Calculate four coefficients (b0, b1, b2, b3) by
  easily-generated equations

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Test of On-Chip DAC
Fitting for INL error
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Design of S? Modulator
a SNR(dB) OSR
1 122.16 75311
2 116.14 47445
4 110.12 29890
8 104.10 18830
16 98.08 11863
3 LSB
104.10dB
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Simulation Results for On-Chip DAC
On-chip DAC INL error
Polynomial fitting for INL error
Fitting results through 6-bit dithering DAC
Final analog outputs by calibrated DAC
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Test of On-Chip ADC
INL error
Calibrated DAC to generate linear analog output
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Summary

• A built-in test and calibration scheme for
  on-chip DAC/ADC is proposed
• A polynomial fitting algorithm is used to fix
  non-linearity error of DAC/ADC outputs
• Fault tolerance factor can be chosen for
  different applications
• Simulation results show that linearity is
  significantly improved after calibration
• Future research work
• Reduce the testing time
• Improve the fitting algorithm for even higher
  linearity

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THANKS

• QA