CPRE 594 Embedded Systems Research Skills Lecture 5: Tue 2102008 Xilinx Embedded Development Kit EDK - PowerPoint PPT Presentation

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CPRE 594 Embedded Systems Research Skills Lecture 5: Tue 2102008 Xilinx Embedded Development Kit EDK

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System Generator. 5 - CPRE 594 (Embedded Systems Research Skills): Embedded ... Used to design embedded application that are typically made up of both HW and SW ... – PowerPoint PPT presentation

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Title: CPRE 594 Embedded Systems Research Skills Lecture 5: Tue 2102008 Xilinx Embedded Development Kit EDK


1
CPRE 594Embedded Systems Research SkillsLecture
5 Tue 2/10/2008(Xilinx Embedded Development Kit
(EDK))
Instructor Dr. Phillip Jones (phjones_at_iastate.edu
) Reconfigurable Computing Laboratory Iowa
State University Ames, Iowa, USA http//www.ece.ia
state.edu
http//class.ece.iastate.edu/cpre594/ and WebCT
2
Outline
  • Class Wiki!!
  • Discuss System Generator
  • Edge Detection Progress
  • Interesting Features
  • EDK Introduction
  • MemoCODE (2008) Challenge
  • Assignment

3
Wiki
  • Whats new!

4
System Generator
  • Edge Detection Results
  • Interesting Features
  • Update Looks like will have to use JTAG
    interface instead cool high-speed Ethernet
    interface for HW/SW co-simulations.

5
Xilinx Embedded Design Kit (EDK)
  • Used to design embedded application that are
    typically made up of both HW and SW components

DRAM
DMA
Application Logic
PowerPC 440
Bus
UART (Serial)
6
Xilinx Embedded Design Kit (EDK)
  • Environment for SW development
  • Environment for import Hardware components
  • Environment for simulating HW and SW

DRAM
DMA
Application Logic
PowerPC 440
Bus
UART (Serial)
7
Xilinx Embedded Design Kit (EDK)
  • First Project
  • Echo UART using PPC software (in HW)
  • Echo UART using PPC Echo FIFO (simulate first,
    do not use UART during simulation!!)

DRAM
DMA
Application Logic
PowerPC 440
Bus
UART (Serial)
8
Xilinx Embedded Design Kit (EDK)
  • First Project
  • Echo UART using PPC software (in HW)
  • Echo UART using PPC Echo FIFO (simulate first,
    do not use UART during simulation!!)

DRAM
DMA
Application Logic
PowerPC 440
Bus
UART (Serial)
9
Xilinx Embedded Design Kit (EDK)
  • First Project
  • Echo UART using PPC software (in HW)
  • Echo UART using PPC Echo FIFO (simulate first,
    do not use UART during simulation!!)

DRAM
DMA
PowerPC 440
FIFO
Bus
FIFO
UART (Serial)
10
Xilinx Embedded Design Kit (EDK)
  • First Project
  • Use EDK with minimum VHDL knowledge
  • CoreGen (Create needed FIFOs)
  • ISE (Minimum VHDL to connect FIFOs)
  • Use EDK to import connect FIFOs into project

11
Xilinx Embedded Design Kit (EDK)
  • Documentation (see class webpage)
  • EDK Reference Manual
  • Use Linux Machines in 2048 to run Xilinx tools.
    Use Linux machines in 2041 to test designs in HW
    (or you can use xilinx.ece)

12
MemoCODE 2008
  • See 2008 Contest Website
  • http//memocode.irisa.fr/2008/designcontest08
  • Cryptosorter
  • See course webpage for 2008 reference example
    (Note you will have to port this to the ML507 or
    ML509)

13
Assignment
  • Groups of 2-3
  • EDK
  • Review documentation
  • First Project PPC and echo FIFO
  • 3-5 slides on EDK work
  • Draft to me by Monday Midnight.
  • MemoCODE (2008)
  • 3-5 slides on thoughts, implementation (unless
    all time spent on EDK first project)
  • Draft to me by Monday Midnight
  • Next week
  • More EDK
  • Extend First Project, discuss ways you may have
    already extended it Some VHDL review
  • Lots of Cryptosorter disscussion
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