InstructionLevel Parallelism for LowPower Embedded Processors

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Instruction-Level Parallelism for Low-Power
Embedded Processors
Ph.D. Thesis Jean Michel Puiati, EPFL

• January 23, 2001
• Presented By
• Anup Gangwar

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Introduction

• Need for high performance low power processors
• Synergistic hardware -compiler design for EPIC or
  VLIW like architectures
• A new variable instruction length scheme
• Full predication support in hardware

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Outline

• Instruction-Level Parallelism
• Power Consumption in VLSI Circuits
• A Look at Available Mobile and DSP Processors
• High-Level Evaluation of A Low-Power VLIW
  Processor
• The DEVIL Low-Power Processor
• A Step Towards Predicated Execution
• Conclusion

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ILP Concepts and Limitations

• Data Dependences
• Flow Dependence or RAW
• Anti Dependence or WAR
• Output Dependence or WAW
• Reduction of critical path
• Control Dependences
• Resource Conflicts

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Achieving ILP Pipelining

• Control dependencies affect pipelined execution
• Data dependencies affect pipelined execution
• Resource conflicts affect pipelined execution

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Achieving ILP Superscalar
Architectures

• In-order issue with in-order completion
• In-order issue with out-of-order completion
• Out-of-order issue with out-of-order completion

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Achieving ILP VLIW Processors

• Low circuit overhead than Superscalar Processors
• Limited number of resources
• Explicit insertion of NOPs increases code size

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Extracting ILP BasicBlock Scheduling
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Extracting ILP Superblock Scheduling
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Extracting ILP Predicated Execution
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Power Consumption in CMOS Circuits Parallelism
for Energy Efficiency
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Available Mobile and VLIW Processors

• The ARM Family
• The ARM7 Generation
• The StrongARM
• The ARM Thumb Option
• The ARM Piccolo Option
• The ARM9 and ARM10

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Available Mobile and VLIW Processors

• The Motorola M-Core
• The LSI TinyRisc
• The Hitachi SuperH Family
• VLIW Processors
• The Motorola-Lucent StarCore
• The Philips TriMedia
• The HP/Intel IA-64

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High Level Evaluation of A Low-Power VLIW
Processor

• Energy consumption distribution

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High Level Evaluation of A Low-Power VLIW
Processor

• NOP Elimination in VLIW Processor

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High Level Evaluation of A Low-Power VLIW
Processor

• Speed-up Comparison

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High Level Evaluation of A Low-Power VLIW
Processor

• Energy Comparison

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High Level Evaluation of A Low-Power VLIW
Processor

• Energy-Delay Product Comparison

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The DEVIL Low-Power Processor

• Complexity in VLIW Architectures
• Hardware Duplication
• FUs and number of registers as well as ports
• Number of FUs versus type of FU
• Number of FUs versus available ILP

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The DEVIL Low-Power Processor

• Code Memory

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The DEVIL Low-Power Processor
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The DEVIL Low-Power Processor

• Instruction Fetch Mechanism

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The DEVIL Low-Power Processor

• Branch Prediction Mechanism

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The DEVIL Low-Power Processor

• Performance with and without superscalar
  optimizations

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The DEVIL Low-Power Processor

• Effect of SuperScalar optimization on code size

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The DEVIL Low-Power Processor

• Effect of NOP elimination on code size

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The DEVIL Low-Power Processor

• Effect of NOP elimination on the number of
  accesses to code memory

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The DEVIL Low-Power Processor

• Effect of instruction fetch mechanism on code size

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The DEVIL Low-Power Processor

• Code size comparison with existing mobile
  processors

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A Step Towards Predicated Execution

• Compiler techniques for reducing predicate code
  size
• Reduction of number of Control Instructions
• Predicate promotion and Instruction merging
• Instruction reduction for advanced code generation

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A Step Towards Predicated ExecutionReduction of
number of Control Instructions
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A Step Towards Predicated Execution Predicate
promotion and Instruction merging
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A Step Towards Predicated Execution

• Introducing predication support into processor
• Effect on code size of full predication
• Predication code size and Execution
  Characterstics
• Prefix based predication

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A Step Towards Predicated Execution

• Relative number of predicated instructions

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A Step Towards Predicated Execution

• Code expansion considering predication

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A Step Towards Predicated Execution

• Code reductions due to predicated execution

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Conclusions

• A synergistic hardware-compiler approach for
  low-power processors
• A new VLIW architecture to reduce increase in
  code size
• A prefix based predicated execution architecture
  framework