The Level 0 trigger decision unit (L0DU) for the LHCb experiment

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The Level 0 trigger decision unit (L0DU) for the
LHCb experiment

• Julien Laubser, Hervé Chanal, Rémi Cornat,
  Emmanuel Delage,Olivier Deschamps, Magali Magne,
  Maxim Matemiyanov, Pascal PerretLaboratoire de
  Physique Corpusculaire de Clermont-Ferrand

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Outline

• System overview - the LHCb experiment - the
  Level 0 trigger system - input/output and
  setup
• The L0DU - L0DU board design - the test bench
• - board layout
• The L0DU processing - algorithm requirements -
  flexible architecture - L0DU system and status
• Conclusion

The Large Hadron Collider (LHC) accelerator CERN
The LHCb cavern
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PART ISystem overview
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LHCb experiment

• AimMeasure the CP violation in B decays
• Proton/proton collisions occur _at_ 40 MHz
• Due to the high quantities of produced data, an
  on-line selection system of interested events is
  implementedgt The trigger system
• A specific channel for the Data Acquisition
  (DAQ)
• The trigger system is composed of- an hardware
  level, Level 0 trigger custom
  electronics synchronous pipeline architecture
  - a software level, High Level Trigger (HLT)

Layout of the LHCb spectrometer
Collision
40 MHz
Level 0
1 MHz
L0DU
HLT
2 kHz
Store the filtered eventfor offline analysis
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Overview of the L0 trigger

• Composed of four custom processors- L0
  Calorimeter trigger, the L0 Muon trigger, the L0
  Pile-Up system and the Level 0 Decision Unit
  (L0DU)
• Reduce the data flow down to 1 MHz for the next
  trigger level
• A physics algorithm is applied to select events
  and to deliver the L0DU decision
• System fully synchronous, pipeline
  architecturegt each event is processedgt a
  decision is produced every 25 ns and the system
  is able to generate consecutive triggers
• Each L0 sub-trigger has a fixed latencygt
  synchronization with the local clockgt Data time
  alignment
• Latency budget for the L0DU is 500 ns

Muon sub-detector
Calorimetersub-detector
Pile-Upsub-detector
Pile-UpSystem
CalorimeterTrigger
MuonTrigger
L0DU
1 MHz
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L0DU Input/Output Setup
L0DU Input/Output

• 24 optical inputs at 1.6 Gb/s 5 GBytes/s
• gt Expected input data flow 864 bits _at_ 40
  MHz

• Output Decision word 16 bits _at_ 40 MHz
• DAQ frame 1024 bits _at_ 1 MHz

Twelve links ribbon with female M PO connectors
L0DU Setup

• L0DU is implemented as a plug-in module on a
  standard LHCb DAQ board (TELL1)
• The TELL1 is used for- DAQ output- Experiment
  Control System (ECS) for the slow control -
  power supply- JTAG

TELL1
ECS
DAQ
L0DU
L0DU plugged on a TELL1
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PART IIThe L0DU board
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Board Design
Control FPGAEP1S10-F780
ECS accessfor slow control
DAQ Output1024 bits _at_ 1 MHz
Processing FPGAsEP1S60-F1020
Ext. Static RAM
It centralizes the L0 trigger datato compute the
L0DU decision
Ext. Static RAM
EPC16
// Bus com
216 bits_at_ 80 MHz
216 bits_at_ 80 MHz
TTC
12 Deserializers
12 Deserializers
Clock referencenetwork
USB Interface(Lab. Slow control)
16 bits_at_ 40 MHz
121.6Gb/s
121.6Gb/s
Timing and Trigger Control mezzanine
Optical Transceiver
Fiber Ribbon
Fiber Ribbon
Decision Output
L0 trigger processor data
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L0DU Test bench

• High reliability is required as the L0DU is the
  central system of the L0 trigger system
• The test of the L0DU and the test bench are also
  complex than the unit itself
• A Specific pattern injection (GPL) has been
  developed to be able to emulate the
  L0sub-triggers and to characterize the links
  used.

• Allows to- Characterize the links and the
  optical design- Emulate the L0 sub-triggers
  outputs

FPGA
Static RAM
212 Désérialiseurs
121.6Gb/s
Decision Input
PCB 16 layers class 6
Optical Transceiver
Slow controlvia USB
TTC
121.6Gb/s
Eye diagram for a 1.6 Gb/s optical link(with 0
dB of attenuation)
The GPL board with dual characteristic to the
L0DU
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Board Layout
12 mm

• Layout complex due to - high density of
  signals - frequency of the signals 1.6 GB/s
  (tr,tf 110 ps), 80 MHz (tr,tf 1 ns),
• Must follow specific design rules for high speed
  signals, clock and power supply- keep trace as
  short as possible- controlled impedance- keep
  the trace identical between the differential
  signals to prevent signal skew
• All the critical parts of the PCB layout have
  been simulated- interconnexion between
  transceivers and deserializers- interconnexion
  between deserializers and FPGA- interconnexion
  bus between the two processing FPGA
• PCB 16 layers class 6
• Optical design areagt 100mm x 200mm (32 of
  total area)

Transceivers gt Deserializers
Length (mm) Width (mm) Depth (mm)
366.7 170 2
FPGA gt FPGA
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PART IIIL0DU Processing
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L0DU algorithm requirements

• Algorithm- based on multiple conditional
  choices based on physics criteria- each
  condition is composed by arithmetic and logical
  operators
• L0DU architecture must be flexible in order to
  set up the decision algorithm without FPGA
  reprogramming
• Two notions- Configurable gt the architecture
  must allow to select the input of the decision
  algorithm and the logical operators -
  Parameterizablegt the architecture must allow
  to parameterize the thresholds
• The principle is based on pre-synthesized logic
  cellsthat are selected by switching matrix
• Limitation due to the amount of pre-synthesized
  logic cells and the size of the FPGA gt Stratix
  EP1S60-F1020 in BGA package
• Use of a dedicated software which represents the
  L0DU algorithm
• gt Configuration and parameterization via the
  control interface

FPGA principle design
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Flexible architecture

• Flexible architecture due to- data fan-out and
  input selection via a switching matrix-
  configurable thresholds stored on internal
  registers- selectable arithmetic operators (gt,
  lt, , , ?) via registers- use of a
  Programmable Logic Device (PLD) structure based
  on AND and OR network to set up the trigger
  channels gt easy to add new trigger channels

Data fan-out
New data Production
Logical operator Selection
AND Network

• In addition - monitoring functions for on-line
  monitoringgt counters associated to sub-trigger
  channelgt counters associated to L0DU
  decisiongt error counters - an internal test
  bench is implemented to check the behaviour of
  the L0DU in the pit - the memories of the
  internal test bench can be used to store the L0
  trigger data (spy mode)

Rate division of the trigger channel
OR Network
Decision
Decision foronline study
L0DU flexible architecture
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L0DU system

• The L0DU system is fully operational - board
  tested and validated at Laboratory and in the
  LHCb pit - software control interface
• The control interface allows to - configure and
  parameterize the L0DU algorithm gt new trigger
  channel could be added easily - run specific
  functionalities for commissioning - configure
  the pattern injection board - monitor the
  behaviour of the L0DU - test the full path of
  the system
• Software development will concern the monitoring
  tools of the L0DU
• The L0DU control system has been integrated in
  the global control system of the LHCb detector

Elementary condition definition panel
Trigger rate monitoring panel
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L0DU commissioning

• The board is being used during the commissioning
  of the LHCb detector - commissioning of the DAQ
  path - commissioning with the Timing and Trigger
  Control system - commissioning with the muon
  trigger processor - commissioning with the
  calorimeter trigger processor
• A full trigger path combined with a DAQ is under
  commissioning with the Calorimeter and the L0DU
• The final board (2007) has been received at the
  beginning of February
• All the functionalities and links have been
  tested and qualified at laboratory, and all the
  final board are under production
• The L0DU system is ready for the commissioning
  phase

Board crate at laboratory
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Conclusion

• The PCB, the L0DU interfaces and the
  functionalities have been tested and validated
• A flexible trigger architecture has been
  developed and allows to provide a new tool to
  the particle physics
• The processing of the FPGA have been tested with
  the GPL board
• Board layout complex due to the high frequency
  and the high density of signals
• Many Specctra Quest simulations must have been
  done before manufacturing and allow to make a
  such design without hardware failure
• The board is being used for the LHCb detector
  commissioningphase and the system will be
  operational for engineering run

L0DU board at the LHCb pit