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Leakage Modeling and Reduction Amit Agarwal, Lei He et. al

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Title: Leakage Modeling and Reduction Amit Agarwal, Lei He et. al


1
Leakage Modeling and ReductionAmit Agarwal, Lei
He et. al
  • Presenters Qun Gu
  • Ho-Yan Wong
  • Courtesy of Lei He

2
Outline
  • Introduction
  • Circuit level leakage reduction
  • System level leakage reduction
  • Coupled leakage and thermal simulation and
    management

3
Power Trends
4
Circuit Power
  • Dynamic Power determined by circuit performance
    requirement etc. The percentage is getting
    smaller.
  • Short_Circuit Power Both PU and PD circuit
    partially conduct. Small percentage. (lt10)
  • Leakage Power Increasingly important, and many
    issues dependent, such as device geometry,
    temperature, doping, processing and data pattern
    dependent, etc. It is very complicated and worthy
    to study more to improve it.

5
Leakage Power Sources
  • Subthreshold leakage
  • Reverse Biased Junction BTBT Leakage
  • Gate Leakage

6
Leakage Dependences
7
Circuit Techniques to Reduce Leakage
  • Design Time Techniques
  • Dual threshold CMOS
  • Run Time Techniques
  • Standby Leakage Reduction Techniques
  • Natural Transistor Stacks
  • Sleep Transistor (MTCMOS)
  • Forward/Reverse Body Biasing (VTCMOS)
  • Active Leakage Reduction Techniques
  • Dynamic Vth Scaling (DVTS)

8
Dual Threshold CMOS
  • Adjust Vth approaches in fabrication
  • Adjustment of tox (the higher tox, the higher
    Vth)

How?
  • Low Vth for critical path
  • High Vth for non-critical path
  • Concerns
  • It is not so straigtht forward to do this.
    Sometime tradeoff exist between high Vth and low
    Vth applications.
  • Vth variation cannot be always success at low
    voltage supplies.
  • Increasing the number of critical paths will
    sometimes hurt circuit performance.

9
Natural Transistor Stacks
How?
  • Reduce the leakage by stacking the devices.

Concerns
  • Trade off between speed and power
  • Data pattern determined
  • Trade off with other leakage power ( gate
    leakage)

10
Sleep Transistor (MTCMOS)
11
Improvements for MTCMOS -- VRC
  • Virtual power/ground Rails Clamp (VRC)
  • Solves data retention problem with diodes
  • Virtual level changes are clamped
  • Allow data to be retained in SRAM arrays
  • Alternatives Super cutoff CMOS (with low Vth)
    (SCCMOS)
  • In standby mode, PMOS gate is Vcc0.4v, NMOS is
    Vss-0.4v to fully cut off leakage.

12
Forward/Reverse Body Biasing (VTCMOS)
FBB (Forward Body Bias) high Vth in standby
mode, forward body biasing to achieve better
current drive in active mode.
RBB (Reverse Body Bias) zero body bias in active
mode, a deep reverse bias in standby mode.
  • Disadvantages
  • Larger junction capacitance
  • High body effect for stack devices
  • Disadvantages
  • Increase PN junction reverse leakage
  • Scaling down technology worsen short channel
    effects and weaken the Vth modulation capability
  • Technology improvement for high Vth
  • Different doping profile
  • Higher work function materials

13
Dynamic Vth Scaling (DVTS)
How?
  • When critical path replica frequency is less
    then reference CLK, adjust bias to decrease Vth.
  • Otherwise adjust bias to increase Vth.

Results
  • The lowest Vth is delivered (NBB-no body bias)
    if the highest performance is required.
  • When the performance demand is low, clock
    frequency is lowered and Vth is raised via RBB to
    reduce the run time leakage power dissipation.

14
Process Variation and Leakage
  • Variation Sources
  • Channel length
  • Transistor width
  • Oxide thickness
  • Flat-band voltage
  • Random dopant effect
  • The effects of larger spread of leakage
  • Robustness of logic circuits.
  • Circuit design margin.

IDSAT and IOFF variation measured (150nm
process).
  • Circuit Techniques for Compensation Process
    Variation
  • Adaptive body biasing for process compensation
  • Process variation compensation in dynamic
    circuits

15
Adaptive Body Biasing for Process Compensation
16
Process Variation Compensation in Dynamic
Circuits (I)
Dynamic Circuits need keepers to compensate
leakage current to keep data.
  • The consideration for keepers size
  • Unnecessary large keeper size will hurt circuit
    performance
  • Excess leakage dies can not meet the robustness
    requirements without enough keeper size.

Programmable keeper size scheme A desired
effective keeper width can be chosen among 0, W,
2W, 7W according to the control bit.
17
Process Variation Compensation in Dynamic
Circuits (II)
  • Simulation Results
  • 5X reduction in the number of robustness failing
    dies and 10 improvement in average performance.
  • Variation spread of the robustness and delay
    distribution is reduced by 55 and 35

18
System Level Leakage Reduction
  • Motivation
  • Leakage characteristics and reduction
  • Coupled leakage and thermal simulation and
    management
  • Power and thermal simulation
  • Dynamic power and thermal management
  • Vdd scaling with cooling selection

19
Motivation
  • Leakage current has increased due to scaling in
    Vt, L, and tox
  • Leakage power becomes more important due to high
    leakage devices and low activity rates
  • Leakage power depends greatly on temperature

20
Power States at System Level
  • 3 Power states defined at system level
  • Active Mode circuit in operation
    P Pd Ps
  • Standby Mode circuit is idle but ready to
    execute P Ps
  • Inactive Mode circuit is deactivated by leakage
    reduction techniques P lt Ps

21
System Level Leakage Power Modeling
  • Early model
  • Ps Vdd N FET k design Ileakage
  • Later model, with application of 2 leakage power
    reduction techniques (later)
  • Ps Vdd Ngate Iavg

22
Leakage Power Characteristics
  • Minimum Idle Time (M.I.T)
  • M.I.T. Es-i Ei-s Pi (ts-i ti-s) / (Ps
    Pi)
  • Idle Period
  • Leakage power reduction is useful only when Idle
    Period gt M.I.T.

23
Runtime Leakage Reduction for Caches
  • Caches dissipate large amount of leakage power
    due to large SRAM array structures
  • Different techniques are developed to reduce L1
    cache Ps, e.g. DRI, SWAY
  • Basic principle is to dynamically turn off
    partial cache array structure

24
Ps Reduction for L2 Caches
  • L2 cache has much larger miss penalty, so
    approach for L1 can not be directly applied
  • Use VRC to reduce Ps , and use time-out based
    control mechanisms to shutdown L2-cache data
    portion
  • Time out threshold could be fixed (FTO), dynamic,
    or by feedback control (FCTO)

25
Ps Reduction for L2 Caches contd
  • FTO
  • Time out threshold is set as M.I.T.
  • FCTO
  • Adjust the time-out threshold with the
    proportional-integral (PI) feedback controller
  • Update time-out threshold according to
  • N L2 cache miss rate in previous time window
  • Told Time-out threshold in previous time window
  • New timeout threshold T Told (N Setpoint)
    Gain

26
Circuits for FCTO
Data word
Request address
Tag
Index
Block offset
Mux
  • Timeout controller
  • Threshold controller

Tag potion
Data potion
hit/miss
Wakeup signal
Yes
Hit?
Wakeup/ shutdown signals
Threshold controller
Check for tag match
Timeout controller

Shutdown signal
Counter
hit/miss
-
X

Nmiss
setpoint
gain
Threshold register
Threshold output
27
Comparison of L2 Leakage Reduction
  • Time-out (FTO and FCTO) achieve much smaller
    performance penalty
  • Targeting at 1 performance loss, FCTO obtains
    more power reduction than FTO does.

Power reduction () Power reduction () Power reduction () Power reduction () Performance penalty () Performance penalty () Performance penalty () Performance penalty ()
Benchmark FTO FCTO SWAY DRI FTO FCTO SWAY DRI
go 52.21 63.80 57.55 56.79 1.06 1.10 9.95 7.39
li 12.92 27.87 26.64 26.56 0.93 1.07 7.28 7.71
equake 35.75 48.61 46.40 45.71 0.84 1.01 9.73 10.58
art 0.07 2.20 2.17 2.18 0.37 0.92 3.18 3.14
28
System Level Leakage Reduction
  • Motivation
  • Leakage characteristics and reduction
  • Coupled leakage and thermal simulation and
    management
  • Power and thermal simulation
  • Dynamic power and thermal management
  • Vdd scaling with cooling selection

29
Temperature Aware Computing
Initial conditions (T, delay)
Performance simulator (e.g. SimpleScalar, IMPACT)
uArch Floorplan packaging
Dynamic power estimation (e.g. Wattch)
Leakage estimation
Coupled power and thermal simulator (e.g.
PTscalar, PowerImpact)
Workload (e.g. Spec 2k)
Temperature-aware architecture techniques (DVS,
DTM, reconfigurability power model, GALS, etc)
Adjusted conditions (T, delay)
30
Leakage Model with Temperature Scaling
  • Exponential scaling based on BSIM3v3
  • Logic circuits in ITRS 100nm technology
  • Memory units in ITRS 100nm technology

31
Delay with Vdd and Temperature Scaling
  • Based on SPICE level 1 model, transistor
    saturation current Isat is proportional to
  • We obtain
  • ITRS 100nm technology

32
Thermal Modeling
  • For the lumped RC thermal circuit
  • Thermal resistance Rth the ability to remove
    heat to the ambient in steady-state condition
  • Thermal capacitance Cth capture the delay
    between a change in power and the corresponding
    change in the temperature
  • Thermal time constant t Rth Cth
  • Distributed model is needed for accurate solution

33
Coupled Power and Thermal Simulation
  • Simulate time step ts lt 0.5 of time constant
    (106 cycles) will give negligible temperature
    and power calculation errors
  • Clock gating reduces dynamic power and also
    leakage energy
  • Leakage energy changes with operation temperature

34
Leakage Power at Different Temperature
100
100nm, 3.33GHz, 1.2V
80
60
Normalized total power
40
20
0
35
85
110
Dep
35
85
110
Dep
Benchmark art
Benchmark gcc
Temperature (oC)
Dynamic power
Leakage power
  • uP similar to DEC Alpha 21264 and with clock
    gating
  • Leakage differs by up to 2X between 80oC and
    110oC
  • Differs for different applications too.
  • Coupled thermal and power simulation is a must

35
Thermal Runaway
  • Thermal runaway is caused by the positive
    feedback loop between on-resistor, temperature,
    and power
  • Also a result of the interaction between leakage
    power and temperature
  • Component temperature ??leakage power ?
    exponentially ? temperature ?
  • If cooling not adequate, both keep increasing

36
Thermal Runaway contd
  • Assume no throttling and constant power
    consumption, conditions for thermal runaway is
    equivalent to d2T/dt2 gt 0
  • Lowest temperature to meet TR criteria is runaway
    temperature

37
Dynamic Power and Thermal Management (DPTM)
  • Goal Maximize throughput subject to maximum
    on-chip temperature constraint
  • For each time window X cycles, stop or
    throttle instruction fetch in cycles
  • 0ltd lt1
  • Feedback controller (Proportional Integral) to
    adjust d
  • For each time window, updated according to
  • Current maximum on-chip temperature
  • d in previous time window

38
Dynamic Power and Thermal Management (DPTM)
  • Fetch toggling toggles I-cache, I-TLB, branch
    prediction and decode units
  • Dynamic frequency scaling (DFS) and Dynamic
    Voltage Scaling (DVS) adjust the clock freq and
    Vdd ? stall
  • Activity migration move activities to another
    component copy of lower temperature

39
Need for Temperature Dependent Leakage Model
  • Dynamic thermal management using fetch toggling
    with PI feedback controller
  • Implemented 2 models simple (fixed Ps) and
    accurate (Ps is temp. dependent)

40
Validation of PI-based DPTM
  • Compared with two practices
  • No dynamic management
  • Lower Vdd to avoid thermal violations
  • Cooling down
  • If reaching the thermal threshold, stop the whole
    processor until the maximum temperature is X oC
    lower than the threshold
  • X 5 in our experiments

41
System Performance
  • DPTM by feedback control may improve throughput
    by up to 11 compared to no DPTM case
  • DPTM allows designing for common workload but not
    the worst case gt thermal speculation

42
Active Cooling
  • Direct water-spray cooling
  • Thermal resistance 0.067 compare to 0.8 for
    conventional heatsink
  • Microchannel with liquid coolant,

43
Impacts of Water Cooling
  • Increases the maximum throughput by 30
  • Improves power efficiency by 9 and slows down
    the decay of power efficiency

44
References
  • Amit Agarwal et. al, Leakage Mechanisms and
    Leakage Control for Nano-Scale CMOS Circuits,
    Purdue University.
  • Lei He et. al, System Level Leakage Reduction
    Considering the Interdependence of Temperature
    and Leakage, UCLA.

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