ECE345 Senior Design Project

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ECE345 - Senior Design Project

• Brad Bozeman, David Crook
• Design Verification of FPU for DLX Model

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Project Goals

• Modify verification environment to encompass
  Floating Point instructions
• Implement Floating Point instructions in a
  hardware description

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Description

• Modified generator/ verification environment
  (C) to include Floating Point instructions
  (previously only contained integer instuctions)
• Verify correct implementation (VHDL) of set of
  Floating Point instructions in a hardware
  description.

FOR MORE INFO...

• Contact Dave Crook or Brad Bozeman
• or consult 1998 M.S Thesis of Ta-Chung Chang. A
  Design Verification Environment . . .

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Compelling Reasons for Project

• Floating point numbers (also called reals) are
  used in real-world scientific or calculation
  applications.
• Provide higher precision numbers
• Large number of special cases must be verified
• precision, rounding, over/underflow
• Random instruction test generator can provide a
  golden model to compare

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Important components

• Bias Instruction Test Generator (BITG)
• random instruction test generator written in C,
  OOP (Object-oriented)
• IEEE-754 Floating Point Format
• widely adopted FP representation
• DLX five-stage pipeline model
• written in VHDL-- a common HDL (Hardware
  Description Language)

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Team/Resources

• Utilized EWS workstations/software
• HP Apollo workstations (parser only installed on
  this platform)
• HPs CC compiler (target of existing code)
• Mentor Graphics Renoir Design Suite (on Suns)
• C code and VHDL code from Thesis
• Vikram Iyengar, outside contact

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Procedures

• Partitioned project
• Dave lt-gt BITG
• David only currently in ECE312, VHDL model
  closely resembled solution to final MP in that
  class, was restricted from viewing code
• Brad lt-gt VHDL behavioural model
• Brad had already taken ECE312, was comfortable
  working with VHDL model

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IEEE-754 ISA
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BITG Organization
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VHDL Model

• VHDL model organization

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Schedule (Brad)

• Understand (15 hr)
• how VHDL model was implemented
• built-in VHDL constructs for FP formats
• how to use Renoir design tool
• Implement (gt70 hr)
• necessary control signals/ signal generation in
  VHDL
• blocks for additional pipeline functions
• VHDL for carrying out FP Arithmetic

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Schedule (Dave)

• Understand ( 30 hr)
• FP instructions/format FP representation
• C structure in instruction generator
• Plan/Design/Implement Code (70 hr)
• necessary support components into C structure
• all instruction characteristics into C
  Programmer model
• add capability to input file parser

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Current Status

• C instruction test generator
• Completed instruction generator implementation
  for instructions
• VHDL Behavioral model
• necessary control signals/blocks added
• basic compare, arithmetic operations work
• still needs to add macro-operations (like
  mult/div)

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Unexpected issues over project

• VHDL builtin types
• would not work as planned, required total
  overhaul of code
• code was rewritten from scratch to simulate
  arithmetic algorithm
• Golden model not IEEE-754 at first
• found a compile-time library that was IEEE-754
  conforming- did not have to discard 3500 written
  lines of my C code

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Cost (time)

• combined labor
• 185 hours _at_ 25/hr 4625
• software/hardware
• workstations unknown reference books 100
• software license for Mentor Tools unknown
• post mortem labor
• 15 hours _at_ 25/hr 375

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summary or cost

• Total cost (labor reference material value)
• (does not include cost of equipment, software
  licenses, or equipment maintenance)

• 5100.00

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questions/answers