The 8088 and 8086 Microprocessors and Their Memory and InputOutput Interfaces'

1
Chapter 8

• The 8088 and 8086 Microprocessors and Their
  Memory and Input/Output Interfaces.

2
8088 and 8086 Microprocessors

• From software point of view, 8086 and 8088 are
  identical.
• Both make use of 16 bit MPU.
• 8088 is fully software compatible with 8086
  (predecessor).
• The key difference between these two is their
  hardware architecture.
• 8086 16 bits data bus.
• 8088 8 bits data bus.
• Both devices can addressed up to
• 1 Mbyte memory via their 20-bit address buses.
• 64 K of byte-wide input-output ports.

3
8088 and 8086 Microprocessors
Pin layout of the 8088 microprocessor
Pin layout of the 8086 microprocessor
4
Minimum-Mode and Maximum-Mode Systems

• 8088 and 8086 can be configured to work in either
  two modes
• Minimum mode.
• Logic 1 at MN/MX input lead.
• Smaller system and contain a single
  microprocessor.
• Maximum mode.
• Logic 0 at the MN/MX input lead.
• This configures 8088/8086 for use in larger
  systems with multiple microprocessors.

5
Minimum-Mode and Maximum-Mode Systems

• Mode-selection feature lets the 8088 or 8086
  better meet the need of wide variety of system
  requirements.
• Pin assignments depend on the mode of operation
  selected.
• The pin functions specified in parentheses
  pertain to a maximum mode system.
• Signals divided into three groups
• Common signals.
• Minimum mode signals.
• Maximum mode signals.

6
Minimum-Mode and Maximum-Mode Systems
Signals common to both minimum and maximum modes
7
Minimum-Mode and Maximum-Mode Systems
Unique minimum-modes signals
Unique maximum-modes signals
8
Minimum-Mode Interface Signals

• In this mode, the 8088/8086 itself provides all
  control signals needed to implement the memory
  I/O interfaces.
• Can be divided into the following basic groups
• Address/Data Bus.
• Status.
• Control.
• Interrupt.
• DMA.

9
Minimum-Mode Interface Signals Address/Data Bus

• Serve two functions
• 8088s Address Bus
• Carries address information to memory and I/O
  ports.
• 20 bits long (A0-A19) memory.
• 16 bits long (A0-A15) input/output.
• 8088s Data Bus
• Carries read/write data for memory, input/output
  data for I/O devices and interrupt type codes for
  interrupt controller.
• 8 bits long (D0-D7) multiplexed with address
  bus AD0-AD7.
• Differences _at_ 8086
• 16 bits data bus lines and multiplexed with
  address bus AD0-AD15.

10
Minimum-Mode Interface Signals Status Signals

• Signal lines A16-A19 of both 8086/8088 are
  multiplexed with S3-S6.
• Output at the same time as the data being
  transferred but on different bus lines.
• Identify which segment register used to generate
  the PA that was output on the address bus during
  the current bus cycle.
• S5 reflects the status of interrupt enable flag.
• S6 is always 0.

11
Minimum-Mode Interface Signals Control Signals

• 8088s Control Signals
• Provided to support the memory and I/O
  interfaces, i.e.
• Indicate whether bus carries valid address bus.
• Determine direction of data being transferred.
• Indicate valid write on the bus.
• Signal when to put data on the bus.
• ALE, DT/R, SSO, IO/M, RD, WR, DEN and READY.
• Differences _at_ 8086
• M/IO replaces IO/M.
• BHE replaces SSO.

12
Minimum-Mode Interface Signals Interrupt and
DMA Interface Signals

• Interrupt Signals
• Related to interrupt.
• INTR and INTA.
• TEST.
• NMI and RESET.
• DMA Interface Signals
• Enable/disable external device to take control of
  the system bus.
• HOLD and HLDA.

13
Maximum Mode Interface Signals

• In this mode, 8088/8086 produces signals for
  implementing a multiprocessor/coprocessor system
  environment.
• Multiple microprocessor exists in the system and
  each executes its own program.
• Some system resources are common to all
  processors ? Global resources.
• Other resources are assigned to specific
  processors ? Local or private resources.
• Facilities are provided for
• Implementing allocation of global resources.
• Passing bus control to other microprocessors
  sharing the system bus.

14
Maximum Mode Interface Signals 8288 Bus
Controller

• 8088 does not directly provide all the signals
  that are required to control the memory I/O or
  interrupt interfaces.
• It outputs 3-bit status code on S0-S2 that will
  identify the type of MPU bus cycle to follow.
• In response, the 8288 generates the appropriately
  timed command and control signals.
• Others control signals output by 8288 are DEN,
  DT/R and ALE ? functions same as in min mode.
• 8288 connects to the 8086 the same way and
  produces the same signals as 8088.

15
Maximum Mode Interface Signals 8288 Bus
Controller
16
Maximum Mode Interface Signals Lock, Queue
Status and Local Bus Control Signals

• Lock Signal ? LOCK
• Use to implement multi-processor systems.
• Lock other processors off the system bus during
  access of common/shared system resources.
• Queue Status Signals
• Tells the external circuitry what type of
  information was removed from the instruction
  queue from the previous clock cycle.
• QS0 and QS1.
• Local Bus Control Signals
• Provide a prioritize bus access mechanism for
  accessing local bus.
• RQ/GT0 and RQ/GT1.

17
Bus Cycle and Time States

• Defined the basic operation that MPU performs to
  communicate with external devices.
• i,e, memory read/write, IO read/write.
• Sequence of events that start with an address
  being output on the system bus followed by
  read/write data transfer.
• Controls are produced to control the direction
  and timing of the bus.
• Consists of at least 4 clock periods (T1-T4)
• i.e write operation
• T1 MPU puts address.
• T2 MPU puts data and maintain through T3 and T4.
• 8088 with 8 MHz system
• Bus cycle duration 125 ns 4 500 ns

18
Bus Cycle and Time States
Bus cycle clock periods
19
Bus Cycle and Time States Idle State

• No bus cycle required _at_ no bus activity takes
  place.
• Each idle state is equivalent to one clock
  period long (T).
• Any number of idle state can be inserted between
  bus cycles.
• Perform when instruction queue is full and does
  not need to read/write operands from memory.

20
Bus Cycle and Time States Wait State

• Can also be inserted into bus cycle.
• Done in response to a request by an event in
  external hardware instead of internal event such
  as full queue.
• READY input signal used for this purpose.
• READY0
• Current bus cycle should not be completed.
• Wait states are inserted and data that were on
  the bus during that time is maintained.
• READY1
• Bus cycle completes.
• Extends the duration of the bus cycle.
• Permit the use of slower memory and I/O devices
  in the system.

21
Bus Cycle and Time States Wait State

• Example 1
• What is the duration of the bus cycle in
  8088-based MPU if the clock is 8 MHz and two wait
  states are inserted?

22
Hardware Organization of the Memory Address Space

• Hardware perspective
• 8088 and 8086s memory address space are
  organized differently
• 8088s memory bank 1M 8
• Addresses ? 0000016 FFFFF16
• A0-A19 (20-bit address) selects the storage
  location to be accessed.
• Data in bytes transferred over data bus lines
  D0-D7.

1M x 8 memory bank of 8088
23
Hardware Organization of the Memory Address Space

• 8086s high and low memory bank
• Even address
• Reside at low bank (512 K bytes).
• Odd address
• Reside at high bank (512 K bytes).
• A1-A19 selects the storage location to be
  accessed.
• Applied to both bank in parallel.
• A0 and BHE used as bank-select signals.
• A0 0?enable low bank
• BHE 0?enable high bank
• D0-D7 data bus
• Transfer data to low bank.
• D8-D15 data bus
• Transfer data to high bank.

24
Bus Cycle and Time States Wait State
High and low memory banks of the 8086
25
Hardware Organization of the Memory Address Space
8088 Byte Transfer

• A0-A19 provide address to the memory bank.
• Byte of data is written/read from specified
  location over D0(LSb)-D7(MSb).
• Byte of data is transferred in one bus cycle.
• 8088 running at 5 MHz with no wait states
• Takes (1/5M) 4 800 ns.

Byte transfer by the 8088
26
Hardware Organization of the Memory Address Space
8088 Word Transfer

• Word of data is transferred in two bus cycles.
• Access LSB located at X address through A0-A19
  and data over D0-D7.
• This is performed during the 1st Cycle .
• 8088 automatically increments the address so that
  it points to the next consecutive byte storage
  location (X1).
• Then second memory bus cycle is initiated.
• 8088 running at 5 MHz with no wait states
• Takes (1/5M) 4 2 1.6 ms.

27
Hardware Organization of the Memory Address Space
8088 Word Transfer
Word transfer by the 8088
28
Hardware Organization of the Memory Address Space
8086 Even-Addressed Byte Transfer

• A0 0 and BHE 1
• Enable low bank and disable high bank.
• Data are transferred to or from the lower bank
  over data bus lines D0(LSb)-D7(MSb).

Even-address byte transfer by the 8086
29
Hardware Organization of the Memory Address Space
8086 Odd-Addressed Byte Transfer

• A0 1 and BHE 0
• Disable low bank and enable high bank.
• Data are transferred to or from the higher bank
  over data bus lines D8(LSb)-D15(MSb).

Odd-address byte transfer by the 8086
30
Hardware Organization of the Memory Address Space
8086 Even-Addressed Word Transfer

• High and low bank accessed at the same time.
• A0 0 and BHE 0
• Enable both banks.
• Bytes of data are transferred to both banks at
  the same time over D0-D7(LSB) and D8-D15(MSB).
• Bytes of an even-addressed word
• Aligned and takes only one bus cycle.

31
Hardware Organization of the Memory Address Space
8086 Even-Addressed Word Transfer
Even-address word transfer by the 8086
32
Hardware Organization of the Memory Address Space
8086 Odd-Addressed Word Transfer

• LSB located at the lower address location in the
  high bank.
• Two bus cycles required.
• During the 1st cycle, access odd byte of word in
  high bank where A0 1 and BHE 0.
• Data are transferred over D8-D15(LSB).
• 8086 automatically increments address so that A0
  0.
• Then a second memory cycle is initiated.
• Data are transferred over D0-D7(MSB).
• Bytes of an odd-addressed word
• Misaligned and takes two bus cycles.

33
Hardware Organization of the Memory Address Space
8086 Odd-Addressed Word Transfer
Odd-address word transfer by the 8086
34
Read/Write Cycle

• Study the sequence of status and control signals
  in which they occur for read/write bus cycles of
  memory.
• Read/write bus cycles consist of four cycles
• Shortest time that the MPU can use for carrying
  out a read/write cycle.

35
Read Cycle 8088 Minimum mode

• T1
• AD0-AD7, A8-A15 and A16/S3-A19/S6.
• 20 bit address ? memory location to be accessed.
• ALE 1.
• Latches addresses.
• IO/M and DT/R 0.
• Memory cycle in progress.
• Data is received.
• SSO 1.
• Data operation.
• IO/M and DT/R and SSO signals are maintained
  throughout all the 4 periods of the bus cycle.
• Early T2
• S3-S6 output on the upper four address bus lines
  A16-A19.
• Identify which segment register was used to
  generate the address just output.
• Maintain through T3 and T4.

Minimum mode memory read bus cycle of the 8088
36
Read Cycle 8088 Minimum mode

• The part of the address output on address bus
  lines A8-A15 maintained through state T2-T4.
• AD0-AD7 are put in the high Z state.
• Late T2
• RD 0
• Read operation cycle in progress.
• DEN 0
• To enable data to be transferred.
• T3
• Data read at this time.
• Memory must provide valid data during T3 and
  maintain it until the MPU terminates the read
  operation.
• T4
• RD 1 ? the read operation terminated.
• DEN 1 to disable data bus.

Minimum mode memory read bus cycle of the 8088
37
Read Cycle 8086 Minimum and Maximum mode

• Differences
• BHE is output along with address during T1.
• The data read by the 8086 during T3 can be
  carried over all 16 data bus lines.
• M/IO which replaces IO/M 1 at the beginning of
  T1 until T4.
• SSO none.
• Address and data transfers that take place are
  identical to 8086s minimum mode read cycle
  except
• S2S1S0 is output just prior to the beginning of
  the bus cycle.
• Later the status is decoded by the 8288 to
  produce control signals ALE, MRDC, DT/R and DEN.

38
Write Cycle 8088 Minimum mode

• Similar to read cycle
• T1
• Address is output and latched with ALE pulse.
• IO/M 0
• Memory cycle is in progress and status
  information is output at SSO.
• DT/R 1
• Transfer data over the bus.
• T2
• WR 0
• Write operation is to follow over the bus.
• Data is put on the bus late in T2 and maintain
  through T4.
• Stop writing data when WR 1
• DEN enables external circuitry to provide a path
  for data from the MPU to the memory.

Minimum mode memory write bus cycle of the 8088
39
Write Cycle 8086 Minimum mode

• Differences
• SSOnone.
• BHE is output along with address.
• The data are carried over all 16 data bus lines.
• M/IO is complement of IO/M.

40
Memory Interface Circuits

• Covers maximum-mode, 8086-based microcomputer
  system.
• Selected instead of 8088 microcomputer because
  8086 is more complex.
• Interfaces include
• 8288 Bus Controller.
• Address Bus Latches.
• Address Decoder.
• Data Bus Transceiver/Buffers.
• Bank Read/Write Control Logic.

41
Memory Interface Circuits
Memory Interface Block Diagram
42
Memory Interface Circuits

• 8088 is simpler since its interface does not
  require bank write control logic.
• Address space organized as single bank.
• Signals S2, S1 and S0 ? inputs to the 8288 bus
  controller.
• Decoded (at 8288) to produce the commands and
  control needed to coordinate data transfers over
  the bus.
• Refer figure 8.20 for status codes.
• i.e. S2S1S0 101
• Memory read bus cycle is in progress.
• MRDC 0 and applied to bank read control logic.

43
Memory Interface Circuits Address Bus Latches

• A0-A19 signals are latched with BHE.
• A17L-A19L ? decoded to produce CE0-CE7.
• ALE (8288) ? CLK input of the address bus latch.
• A1L-A16L ? applied directly to memory subsystems.
• 74F373
• used to implement address latch section for
  8086s memory interface circuits.
• Inputs 1D-8D, C and OC.
• Outputs 1Q 8Q _at_ D-type flip-flop.
• The signals from 8086 microcomputer (AD0-AD15,
  A16-A19 and BHE) are latched by address bus
  latch.
• Fix OC 0 to permanently enable latched outputs
  A0L-A19L and BHEL.
• A1L-A16L applied directly to the memory subsystem.

44
Memory Interface Circuits Address Bus Latches
Address Latch Circuit
45
Memory Interface Circuits Address Decoders.

• 74F139 dual 2-line to 4-line decoder used to
  implement address decoder.
• A17L and A18L A B inputs.
• A19L used to enable one of the decoders. When
  enabled, only the output that corresponds to the
  code BA inputs becomes 0.
• A19L (obtained using an inverter) enables the
  second decoder.
• 4 chip enable (CE) outputs generated. Thus two
  decoders used will produce CE0-CE7.
• Besides 74F139, 74F138 is also used.
• Similar to 74F139 except it is a single 3-line to
  8-line decoder.
• When enabled, only the output that corresponds to
  the code CBA inputs becomes 0.
• Advantage ?Does not require extra inverter to
  generate 8 CE signals.

46
Memory Interface Circuits Address Decoders.
Address Decoder Circuit using 74F139
Address Decoder Circuit using 74F138
47
Memory Interface Circuits Data Bus
Transceiver/Buffers.

• Controls the direction of data transfer MPU
  to/from memory.
• Can be implemented using 74F145 octal bus
  transceiver ICs.
• Bidirectional input/output ? A1-A8 and B1-B8.
• DEN (8288) applied at G _at_ EN ? enables buffer/bus
  transfer operation.
• DIR (driven by DT/R) selects direction of data
  transfer (MPUmemory).
• 16 bit data bus 2 devices are required.
• Another function is to buffer the data bus lines.

48
Memory Interface Circuits Data Bus
Transceiver/Buffers.
Data bus transceiver circuit
49
Memory Interface Circuits Bank Read/Write
Control Logic.

• Memory of 8086 is organized as high (upper) and
  low (lower) banks.
• Require separate read/write control signals to
  two banks.
• MWTC, A0L and BHEL generate write control signals
  (WRU/WRL)
• Two or gates are used for this purpose
• MRDC, A0L and BHEL generate read control signals
  (RDU/RDL).
• i.e. write word of data over D0-D15
• Both WRU/WRL 0.

50
Types of I/O for 8088/8086

• Input/output system allows peripherals to
• Provide data or
• Receive results after processing the data.
• Implemented using I/O ports.
• Employs two different types of I/O
• Isolated I/O.
• Memory mapped I/O.
• Method differs in how I/O ports are mapped into
  MPUs address spaces.
• Some microcomputer employs both method.

51
Isolated I/O

• I/O devices treated separately from memory.
• Hardware and software architecture of 8088/8086
  support separate memory I/O address space.
• Can be accessed as either byte-wide or word-wide.
• Can be treated as either independent byte-wide
  I/O ports or word-wide I/O ports.
• Page 0
• Certain I/O instructions can only perform
  operations to ports in this part of the address
  range.
• Other I/O instructions can input/output data for
  ports anywhere in the address space.

52
Isolated I/O
Page 0
Port 1 (16 bit port)
Port 0 (16 bit port)
53
Isolated I/O

• Advantages
• 1 MByte memory address space is available for use
  with memory.
• Special instructions have been provided in the
  instruction set of 8088/8086 to perform isolated
  I/O input and output operations.
• These instructions have been tailored to maximize
  I/O performance.
• Disadvantages
• All input and output data transfers must take
  place between AL or AX register and the I/O port.

54
Memory-mapped I/O

• I/O devices is placed in memory address space of
  the microcomputer.
• The memory address space is assigned to I/O
  devices.
• MPU looks at the I/O port as though it is a
  storage location in memory.
• Make use of instructions that affect data in
  memory rather than special input/output
  instructions.

55
Memory-mapped I/O
I/O addresses
Port 1 (16 bit port)
Port 0 (16 bit port)
56
Memory-mapped I/O

• Advantages
• Many more instructions and addressing modes are
  available to perform I/O operations.
• I/O transfers can now take place between I/O port
  and internal registers other than just AL/AX.
• Disadvantages
• Memory instructions tend to execute slower than
  those specifically designed for isolated I/O.
• Part of the memory address space is lost.

57
Isolated Input/Output Interface

• The interface permits 8088/8086 microcomputers to
  communicate with the outside world.
• The interface between MPU and I/O is similar to
  MPU and memory.
• Input output data transfers also take place over
  the multiplexed address/data bus.
• Through this I/O interface, the MPU can input or
  output data in bit, byte or word (8086) formats.

58
Isolated Input Output Interface Minimum-mode
Interface
Minimum-mode 8088 system I/O interface
Minimum-mode 8086 system I/O interface
59
Isolated Input Output Interface Minimum-mode
Interface

• Example of I/O device
• Keyboard (input).
• Printer (output).
• Asynchronous serial communications port
  (input/output).
• Circuits in the interface section must perform
  functions such as
• Select I/O port.
• Latch output data.
• Sample input data.
• Synchronize data transfers.

60
Isolated Input Output Interface Minimum-mode
Interface (8088)

• Data/Address Lines
• Multiplexed address/data bus.
• Only 16 least significant lines used.
• AD0-AD7 and A8-A15.
• Control Signals
• Similar to memory interface.
• Difference between 8088 and 8086.
• Complete data bus used for data transfer.
• AD0-AD15.
• M/IO complement of IO/M.
• SSO replaced with BHE.

61
Isolated Input Output Interface Maximum-mode
Interface
Maximum-mode 8088 system I/O interface
Maximum-mode 8086 system I/O interface
62
Isolated Input Output Interface Maximum-mode
Interface (8088/86)

• 8288 bus controller produces control signals for
  the I/O subsystems.
• Decoded S2S1S0 will determine which type of bus
  cycle is in progress.
• If code corresponds to
• I/O read bus cycle , 8288 generates IORC.
• I/O write bus cycle, then IOWC and AIOWC
  generated.
• 8288 also produces ALE, DT/R and DEN control
  signals.
• Data and addresses are transferred over AD0-AD7
  and A8-A15.
• 8086 differs from 8088 as follows
• 16 bit data bus is the path for data transfers.
• Signal BHE is included.

63
Input Output Data Transfers

• Data transfers
• Byte-wide or word-wide.
• I/O address used to select the input/output port
  to be accessed.
• I/O address specified as part of the instruction
  that performs the I/O operation.
• The addresses
• 16 bits in length.
• Output over AD0 (LSb) AD7 and A8-A15 (MSb).
• The most significant address lines A16-A19 0
  during address period (T1) of all bus cycles.
• IO/M determines I/O operations. Held at 1 during
  the complete input/output bus cycles.

64
Input Output Data Transfers

• Data transfer (8088).
• Performed over data bus.
• Byte-wide transfers 1 cycle (D0-D7).
• Word-wide transfers require two bus cycles.
• Two consecutive byte-wide data transfers.
• Data transfer (8086)
• The addresses are output on address/data bus
  lines AD0-AD15.
• A0 and BHE determine whether access at
  odd-addressed byte-wide port, even-addressed
  byte-wide port or word-wide port.
• i.e. A0BHE 10 ? odd-addressed byte wide I/O
  port is accessed.

65
Input Output Data Transfers

• Even and odd addressed byte transfer require 1
  bus cycle.
• Even-addressed byte transfer ? D0-D7.
• Odd-addressed byte transfer ? D8-D15.
• Word data transfer can either require one or two
  bus cycles .
• Word data transfer performed over D0-D15.
• One cycle word transfer ? I/O port is aligned at
  even address boundaries.
• Two cycles word transfer ? Misaligned word.

66
Input Output Instructions

• Isolated I/O mode uses special input and output
  instructions together with I/O port addressing
  modes.
• Can either be direct or variable I/O
  instructions.
• Can be used to transfer byte/word.
• All data transfer take place over I/O device and
  accumulator register (AL/AX).
• Known as accumulator I/O.
• Byte/word wide transfer determined by AL/AX.

67
Input Output Instructions
Input/output instructions
68
Input Output Instructions Direct I/O
Instructions

• Address of the I/O port
• Specified as part of the instruction.
• 8 bits provided for direct address, thus
• Address range is limited to 0016-FF16.
• This range is referred as page 0 in I/O address
  space.
• i.e. IN AL, 0FEH
• (AL) ? (FE16)
• Content of address FE to be input to the AL
  register.
• Only one bus cycle.

69
Input Output Instructions Direct I/O
Instructions

• Example 2
• Write a sequence of instructions that will output
  the data 3416 to a byte-wide output port at
  address 8916 of the I/O address space.

70
Input Output Instructions

• Difference between direct and variable
• The way in which the address of the I/O port is
  specified.
• Direct ? 8 bit address is specified as part of
  the instruction.
• Variable ? use 16 bit address in DX register.
• (DX) is not an offset but actual address.
• Variable I/O instructions can access ports
  located anywhere in the 64 K byte I/O address
  space.
• Data/address must be loaded into or removed from
  AL/AX/DX before another input or output operation
  can be performed.

71
Input Output Instructions

• Example 2
• Write a program that will output DA16 to an
  output port located at address EA2016 of the I/O
  address space.
• Data are to be read in from two byte-wide input
  ports at address AA16 and BA16 and then output as
  a word-wide output port at address B00016. Write
  a program to perform this input/output operation.

72
Input Output Bus Cycles

• Signals (minimum-mode) similar to those involved
  in memory interface.
• Function, logic levels and timing of all signals
  other than IO/M are identical to section 8.11.
• IO/M changes at logic level, not the timing.

73
Input Bus Cycles 8088

• T1
• IO/M 1 and maintained throughout the cycle.
• Indicate IO operation.
• ALE output together with address.
• DEN 0.
• Signals interface circuitry when to put data onto
  the bus.
• 8088 reads data off the bus during period T3.

Input bus cycle of the 8088
74
Output Bus Cycles 8088

• 8088 puts data on the bus late in T2 and
  maintains it during the rest of the bus cycle.
• This time WR 0.
• Signals I/O system that valid data are on the bus.

Output bus cycle of the 8088
75
Input Bus Cycles 8086

• Differences
• BHE output along with address in state T1.
• Used with A0 to select even/odd address byte/word
  wide port.
• Data transfer over 16 bit address/data bus at T3.
• M/IO replaces IO/M.
• SSO none.
• Refer figure 8-53 8-54